Packaging structure for multi-chip stack

Abstract

The invention relates to a sealing structure stacked by multiple chips, which comprises a lead frame, a first chip, a plurality of first metal wires, a second chip, a pair of metal spacing components, a plurality of second metal wires and a sealing body, wherein the lead frame is composed of a plurality of inner leads and a plurality of outer leads, the ends of the inner leads are relatively arrayed at intervals, and the central regions of the inner leads are respectively provided with a radiating fin; the first chip is fixedly connected to the lower surface of the lead frame, and the active surface approaching the central region is provided with a plurality of first welding pads; the first metal wires are used for the electrical connections of the first welding pads with the inner leads;the second chip is fixedly connected to the upper surface of the lead frame, and the active surface approaching the central region is provided with a plurality of second welding pads; the metal spacing components are arranged on the radiating fins of the lead frame and touch the back surface of the second chip; the second metal wires are used for the electrical connections of the inner leads withthe second welding pads.

Description

technical field [0001] The present invention relates to an integrated circuit packaging structure, in particular to a multi-chip stacking packaging structure combined with LOC (Leadon Chip) and COL (Chip on Lead) technologies. Background technique [0002] In recent years, the back-end process of semiconductors has been carrying out three-dimensional (Three Dimension; 3D) packaging in order to use the least area to achieve higher density or memory capacity. In order to achieve this goal, a chip stacked method has been developed to achieve a three-dimensional (Three Dimension; 3D) package at this stage. [0003] In the prior art, for example, U.S. Patent No. 6,744,121 discloses a structure using a lead frame to form a multi-chip stack, such as Figure 1a shown. Obviously, in the package structure shown in Figure 1, in order to prevent the metal wires of the lower chip from contacting the back of the upper stacked chip, the lead frame is bent several times to protect the lowe...

AI Technical Summary

Problems solved by technology

However, the lead frame that has been bent many times is easily deformed, making it difficult to align subsequent chips

In addition, the bent lead frame will make the package structure loose, making it impossible to reduce the package volume

In addition, since the lead frame has been bent many times, the adhesion area between each chip and the lead frame is insufficient, and it is easy to cause the chip to detach during the film injection process.

[0004] In addition, U.S. Patent No. 6,838,754 and U.S. Patent No. 6,977,427 also disclose a structure using a lead frame to form a multi-chip stack, such as Figure 1b and Figure 1c As shown, similarly, in Figure 1b and Figure 1c In all the embodiments, in the process of bonding the upper chip and the lower chip, the back of the upper chip is in contact with the metal wire on the lower chip, causing problems such as short circuit or metal wire peeling.

[0005] In addition, when multiple chips are stacked in a package, the multi-chip stack structure will generate thermal effects during operation; if the thermal effects cannot be quickly discharged out of the multi-chip stack structure, the reliability of the chips will be reduced.

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