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DES encrypted method and its hardware circuit implementing method

An encryption method and encryption circuit technology, applied in the field of cryptography, can solve problems such as large hardware circuit area, and achieve the effects of reducing area, shortening timing critical paths, and reducing circuit power consumption

Inactive Publication Date: 2011-09-14
JINAN UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] At present, the encryption circuit implemented by DES hardware either uses multi-stage cycle technology due to the one-sided pursuit of area minimization, resulting in the need for multiple up to 16 clock cycles to complete plaintext encryption or ciphertext decryption; or due to the one-sided pursuit of speed. Up to 16-stage pipeline technology, resulting in excessive hardware circuit area

Method used

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  • DES encrypted method and its hardware circuit implementing method
  • DES encrypted method and its hardware circuit implementing method
  • DES encrypted method and its hardware circuit implementing method

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Embodiment

[0041] Such as figure 1 As shown, the DES encryption circuit of the present invention includes the following functional modules:

[0042] The main control module used to realize the state control, state decoding, mode selection and other functions of the entire DES encryption circuit and control the key module and the operation module, wherein the main control module receives the Initialstart signal;

[0043] A key module used to receive an initial key from an external circuit, generate a subkey required for encryption or decryption, and transmit the subkey to the computing module;

[0044] An operation module for receiving plaintext or ciphertext data from an external circuit, using the subkey generated by the key module to perform initial permutation, cyclic iteration, and reverse initial circulation of the data to generate the final ciphertext or plaintext;

[0045] Wherein, the key module, the computing module, and the main control module are signal-connected in pairs.

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Abstract

The present invention discloses a DES encryption method, and the realizing method of its hardware circuit. Replacing line connection with shift register to realize initial permutation and inverse initial permutation conveniently; optimizing encryption circuit area and speed by using two stage cycle and two-stage pipeline structure; designing in the way of line connection in the extension / permutation and P permutation in cycle structure for further reducing chip area. The hardware circuit is more suitable to be industrialized in common encryption situation than other DES hardware encryption circuit at present.

Description

technical field [0001] The invention relates to the field of cryptography, in particular to a DES encryption method and a hardware circuit realization method thereof. Background technique [0002] Data Encryption Standard (DES) is currently the most widely used encryption algorithm, especially in the financial field, and was once the de facto world standard for symmetric cryptosystems. At present, in China, with the launch of the Three Gold Project, especially the Gold Card Project, the DES algorithm is widely used in POS, ATM, smart card (IC card), gas station, highway toll station and other fields, thus realizing the confidentiality of key data . [0003] The current exhaustive search attack has greatly threatened the security of DES, but this is only caused by the short key of the DES algorithm, not because of the major flaws in the DES algorithm itself. As long as the length of the key is increased, the encryption circuit implemented by the DES algorithm is still safe....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/06
Inventor 黄君凯张奇潘文明郑观东
Owner JINAN UNIVERSITY