Non-volatile memory device

Abstract

A finFET-based non- volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner- free shape for at least 3 / 4th of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.

Description

technical field [0001] The present invention relates to devices for non-volatile memory applications. The invention also relates to methods of manufacturing such devices. Furthermore, the present invention relates to memory arrays including such devices for non-volatile storage applications, and also to semiconductor devices including such devices for non-volatile storage applications. Background technique [0002] Charge-trapping non-volatile memory devices (NVM devices) such as SONOS (silicon dioxide-silicon nitride-silicon dioxide-silicon) and SHINOS (silicon-high-K-silicon nitride-silicon dioxide-silicon) are considered ) are suitable for implementing flash memory devices in CMOS-era devices at the 45nm node or smaller. SONOS and SHINOS memory devices exhibit relatively reduced programming and erasing voltages. Also, in embedded NVM devices, these devices are relatively easy to integrate with CMOS logic. [0003] Due to short-channel effects, planar NVM devices (typi...

AI Technical Summary

Problems solved by technology

This results in programmed channel regions with locally different threshold voltages; this can degrade the subthreshold characteristics of programmed non-volatile memory devices and subject the (electrical) programming window to significant changes

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