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Method and apparatus for indicating directionality in integrated circuit manufacturing

An integrated circuit, directional technology, applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc.

Active Publication Date: 2013-10-30
NXP USA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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  • Method and apparatus for indicating directionality in integrated circuit manufacturing
  • Method and apparatus for indicating directionality in integrated circuit manufacturing
  • Method and apparatus for indicating directionality in integrated circuit manufacturing

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Embodiment Construction

[0018] figure 1 A cross-sectional view of an integrated circuit 10 is shown that includes an indicator 190 in accordance with one embodiment of the present invention. Integrated circuit 10 includes device 14 with implant direction A and device 16 with implant direction B and indicator 190 , all formed on semiconductor substrate 12 . In one embodiment, implantation direction A may have a first implantation direction and implantation direction B may have a second implantation direction. The semiconductor substrate 12 may be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI) (eg, fully depleted SOI (FDSOI)), silicon, monocrystalline silicon, etc., and combinations thereof .

[0019] In one embodiment, device 14 is an NMOS device and device 16 is a PMOS device, or vice versa. In another embodiment, devices 14 and 16 may both be NMOS or both PMOS, with different asymmetric implant directions. Device 14...

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Abstract

An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Description

technical field [0001] The present invention relates generally to the fabrication of integrated circuits, and more particularly to methods and apparatus for indicating the directionality of an integrated circuit layout relative to the process in integrated circuit fabrication. Background technique [0002] It is desirable to perform an asymmetric halo implant to increase the performance of the device. When various intellectual property (IP) blocks are present, such as SRAM components or microprocessor cores, it may be necessary to verify the correct orientation of the IP blocks so that, if present, they will be in the correct location in each IP block in the correct direction or Orientation performs an asymmetric halo implant. Typically, this verification is done by checking each step of the design data flow between data design and mask design. This is a slow and difficult process, which increases cycle time. Additionally, there is currently no ability to verify orientati...

Claims

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Application Information

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IPC IPC(8): H01L23/544
CPCH01L2223/54453H01L22/34H01L23/544H01L2924/0002H01L2924/00H01L21/67242H01L21/67282H01L21/82
Inventor 爱德华·O·特拉维斯梅于尔·D·施罗夫唐纳德·E·斯梅尔策特拉西·L·史密斯
Owner NXP USA INC