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High voltage PMOS device and production method

A manufacturing method and device technology, applied in the manufacturing field of the high-voltage PMOS device, can solve the problems of device leakage current and breakdown voltage limitation, reduce channel breakdown voltage, large leakage current, etc., and improve driving capability and speed , solve the effect of driving current and breakdown voltage, and increase the driving current

Active Publication Date: 2011-06-01
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to further increase the driving current, it is generally achieved by reducing the thickness of the gate oxide, shortening the channel length, or reducing the resistance of the drift region, but these methods are limited by the leakage current and breakdown voltage of the device.
Moreover, a thinner gate oxide thickness will cause a greater GIDL effect, resulting in a large leakage current; a shorter channel length will reduce the breakdown voltage of the channel; and a lower drift region resistance will reduce the drain terminal junction. breakdown voltage

Method used

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  • High voltage PMOS device and production method
  • High voltage PMOS device and production method
  • High voltage PMOS device and production method

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Embodiment Construction

[0016] In one embodiment, as shown in FIG. 2, the method for manufacturing a high-voltage PMOS device according to the present invention includes the following steps:

[0017] In the first step, the buried trench and P-drift region of the high-voltage PMOS device are formed on the silicon substrate by ion implantation, and the cross-sectional structure at this time is shown in Figure 3a.

[0018] In the second step, a gate oxide layer is grown on the top of the silicon substrate, and the structure at this time is shown in Figure 3b.

[0019] The third step is to deposit a layer of polysilicon gate on the gate oxide layer, and perform N+ ion implantation from the surface of the polysilicon gate, and the dose of implanted ions is 1e15cm -2 ~3e15cm -2 , so that the polysilicon gate becomes an N+ doped polysilicon gate containing only N-type impurities, and the cross-sectional structure at this time is shown in FIG. 3c.

[0020] In the fourth step, the polysilicon gate is etched...

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Abstract

The invention discloses a high-voltage PMOS device and a manufacture method thereof. A double-work-function gate is used to replace the prior single-work-function gate, and the double-work-function gate consists of a P+ doped polysilicon gate part closet to a source-end direction and an N+ doped polysilicon gate part close to a drain-end direction, so as to remarkably increase the drive current of a high-voltage PMOS transistor and then improve the drive capability and speed of the PMOS device under the circumstance of ensuring that the threshold voltage, breakdown voltage, cutoff current andother characteristics of the PMOS device remain the same. Therefore, the contradiction between the drive current and the breakdown voltage is solved.

Description

technical field [0001] The present invention relates to a high-voltage PMOS device with high driving current, and therefore the present invention also relates to a manufacturing method of the high-voltage PMOS device. Background technique [0002] High-voltage PMOS devices usually adopt a buried channel structure, that is, heavily doped N-type polysilicon gates and buried channels are used to improve hole mobility and increase the driving current of the device. In order to further increase the drive current, it is generally achieved by reducing the thickness of the gate oxide, shortening the channel length, or reducing the resistance of the drift region, but these methods are limited by the leakage current and breakdown voltage of the device. Moreover, a thinner gate oxide thickness will cause a greater GIDL effect, resulting in a large leakage current; a shorter channel length will reduce the breakdown voltage of the channel; and a lower drift region resistance will reduce ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/49H01L21/336H01L29/78H01L21/28
Inventor 钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP