Area compact and fast BCH parallel decoding method

Abstract

The invention relates to a quick BCH parallel decoding method with compact area in a control chip of a NandFlash type storage device, and is characterized in that a hybrid arithmetic unit of a finite field GF(2) is multiplexed by the combination of the configuration logic of a control unit of a state machine and the state machine in the multinomial process of iterative operation of wrong position by using one-time multiple-beating manner, and the hybrid arithmetic unit consists of a two-input multiplier and a two-input adder of the finite field GF(2); if the iterative number of rounds is an even number 2k, the hybrid arithmetic unit needs to be multiplexed by 2k+1 times in the round; if the iterative number of rounds is an odd number 2k-1, the hybrid arithmetic unit needs to be multiplexed by 3k+3 times in the round; wherein, k is an integer greater than or equal to 1. In the invention, efficient optimization is carried out by controlling area in a multinomial circuit of error position so that the availability ratio of the hybrid arithmetic unit is maximized, but the reusability is minimized. The method causes better balance of the circuit between area and arithmetic speed, thereby being capable of meeting the requirements of different applied environments.

Description

technical field

[0001] The present invention relates to the error control code technology defined by Bose-Chaudhuri-Hocquenghem (Bose-Chaudhuri-Hocquenghem, namely BCH) code generator, particularly relate to a kind of in the control chip of NandFlash type storage device A compact and fast BCH parallel decoding method. Background technique

[0002] The BCH code is a cyclic code that can correct multiple random errors, and can be described by the root of the generator polynomial g(x). It is a linear block code with strict algebraic structure, strong error correction ability, simple structure, and easier coding than other codes.

[0003] In the control chip of a large-capacity storage device with a NandFlash structure, due to the characteristics of the NandFlash structure and factors such as noise interference, it is inevitable that the transmitted data will be wrong. In order to ensure that error detection and correction can be performed when data is read, usually Both are w...

Examples

Embodiment

[0062] Embodiment: a compact and fast BCH parallel decoding method, by BCH parallel decoding circuit (such as Figures 1 to 4 shown) to realize error correction when reading data, the BCH parallel decoding circuit is mainly composed of adjoint syndrome operation circuit (i.e. figure 1 The adjoint operation circuit in ), the error position polynomial iterative circuit (ie figure 1 The IBM algorithm circuit in the) and the wrong address search circuit (iefigure 1 Chien search circuit in) composition. The BCH parallel decoding circuit works in the finite field GF(2 13 ), first use the syndromic syndrome operation circuit to complete the calculation of the syndrome syndrome through the parallel operation of 8-bit codeword input at the same time, and then use the error position polynomial iterative circuit to obtain The error position polynomial, and finally use the error address search circuit to use the 4-bit pre-search method of full combinational logic to pre-search the error...

technical field

[0001] The present invention relates to the error control code technology defined by Bose-Chaudhuri-Hocquenghem (Bose-Chaudhuri-Hocquenghem, namely BCH) code generator, particularly relate to a kind of in the control chip of NandFlash type storage device A compact and fast BCH parallel decoding method. Background technique

[0002] The BCH code is a cyclic code that can correct multiple random errors, and can be described by the root of the generator polynomial g(x). It is a linear block code with strict algebraic structure, strong error correction ability, simple structure, and easier coding than other codes.

[0003] In the control chip of a large-capacity storage device with a NandFlash structure, due to the characteristics of the NandFlash structure and factors such as noise interference, it is inevitable that the transmitted data will be wrong. In order to ensure that error detection and correction can be performed when data is read, usually Both are w...

Examples

Embodiment

[0062] Embodiment: a compact and fast BCH parallel decoding method, by BCH parallel decoding circuit (such as Figures 1 to 4 shown) to realize error correction when reading data, the BCH parallel decoding circuit is mainly composed of adjoint syndrome operation circuit (i.e. figure 1 The adjoint operation circuit in ), the error position polynomial iterative circuit (ie figure 1 The IBM algorithm circuit in the) and the wrong address search circuit (iefigure 1 Chien search circuit in) composition. The BCH parallel decoding circuit works in the finite field GF(2 13 ), first use the syndromic syndrome operation circuit to complete the calculation of the syndrome syndrome through the parallel operation of 8-bit codeword input at the same time, and then use the error position polynomial iterative circuit to obtain The error position polynomial, and finally use the error address search circuit to use the 4-bit pre-search method of full combinational logic to pre-search the error...

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