Symbol rate hardware accelerator

A technology of hardware accelerator and buffer, which is applied in the direction of instruments, electrical components, digital transmission systems, etc., and can solve problems such as loss of flexibility and changes in hardware requirements

Inactive Publication Date: 2009-07-22
INTERDIGITAL TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional hardware accelerators are typically "hardwired" to perform specific functions, so moving functionality from a DSP to a hardware accelerator will result in a loss of flexibility (compared to running software on a DSP) and if functional requirements arise Changes in the main hardware requirements change

Method used

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  • Symbol rate hardware accelerator
  • Symbol rate hardware accelerator
  • Symbol rate hardware accelerator

Examples

Experimental program
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Embodiment

[0059] CLAIMS 1. A hardware accelerator for performing channel processing on wirelessly transmitted and received information bits, the hardware accelerator in communication with a shared memory.

[0060] 2. The hardware accelerator according to Embodiment 1, comprising: a first buffer and a second buffer for storing information bits and processed information bits.

[0061] 3. The hardware accelerator according to embodiment 2, comprising: at least one address generator for generating addresses for accessing the first buffer and the second buffer.

[0062] 4. The hardware accelerator according to any one of embodiments 2-3, comprising: a translation ROM for generating translated addresses for accessing the first buffer and the second buffer.

[0063] 5. The hardware accelerator according to any one of embodiments 1-4, comprising: an interface for accessing a shared memory.

[0064] 6. The hardware accelerator according to any one of embodiments 1-5, comprising: a CRC generator...

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PUM

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Abstract

The invention relates to a hardware accelerator including a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.

Description

technical field [0001] The present invention relates to wireless communication systems. More specifically, the present invention relates to a symbol rate hardware accelerator for wireless communications. Background technique [0002] A wireless transmit / receive unit (WTRU) for a second generation (2G) wireless communication system typically includes a digital signal processor (DSP) for signal processing and symbol rate processing. A 2G WTRU typically has a control processor (eg, Advanced RISC Group (ARM)) for Layer 1 (L1) control and protocol stack processing. [0003] figure 1 is a block diagram of a legacy WTRU 100 for 2G systems such as Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS) and Enhanced Data Rates for GSM Evolution (EDGE). The WTRU 100 includes: a channel processing unit 110 , a pulse generation and modulation unit 120 , a transmitter 130 and an antenna 140 . The channel processing unit 110 includes: a block encoding unit 1...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00G06F11/00
CPCH04L1/0071H04L1/0043H04L1/0065G06F16/1744G06F9/46G06F13/4022G06F7/5443G06F17/142G06F17/15
Inventor E·L·海普勒
Owner INTERDIGITAL TECH CORP
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