ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)

Abstract

Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application is a continuation of and claims priority to U.S. application Ser. No. 14 / 194,574, filed Feb. 28, 2014, which claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 14 / 187,082, filed on Feb. 21, 2014, which is a non-provisional of U.S. Provisional Application No. 61 / 781,928, filed on Mar. 14, 2013, which are incorporated by reference in their entirety.BACKGROUND OF THE INVENTION[0002]The present invention is directed to computing systems and methods. These computing systems can be applied to communications networks and the like.[0003]Over the last few decades, the use of communication networks exploded. In the early days Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth fo...

AI Technical Summary

Benefits of technology

[0008]Many benefits are recognized through various embodiments of the present invention. Such benefits include having an architecture exhibiting superior power efficiency and in-memory computing efficiency. This architecture can involve disaggregating a large pool of memory (NAND flash or DRAM) that is shared amongst multiple CPU server nodes. Another benefit includes low-latency and high-bandwidth interconnect architecture amongst multiple CPU server nodes. Other benefits will be recognized by those of ordinary skill in the art that the mechanisms described can be applied to other communications systems as well.

Problems solved by technology

In the early days Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small.

Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files.

These limitations provide significant challenges to the continued improvement of communication systems scaling and performance.

Unfortunately, they have been inadequate for various applications.

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