ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)

a shared memory and isma technology, applied in the field of computing systems and methods, can solve the problems of requiring a huge amount of bandwidth, limited popular applications, and large amount of data transfer, and achieve the effect of superior power efficiency and in-memory computing efficiency

a shared memory and isma technology, applied in the field of computing systems and methods, can solve the problems of requiring a huge amount of bandwidth, limited popular applications, and large amount of data transfer, and achieve the effect of superior power efficiency and in-memory computing efficiency

US20160110136A1Inactive Publication Date: 2016-04-21RAMBUS INC
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  • ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)
  • ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)
  • ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)

Examples

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Embodiment Construction

[0014]According to the present invention, techniques are directed to computing systems and methods. Additionally, various embodiments enable separate computer systems having such memory systems to send and receive data to and from other memory systems having such auxiliary interfaces.

[0015]The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0016]In the following detailed description, numerous specific details are set forth in order to provide a more th...

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Abstract

Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application is a continuation of and claims priority to U.S. application Ser. No. 14 / 194,574, filed Feb. 28, 2014, which claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 14 / 187,082, filed on Feb. 21, 2014, which is a non-provisional of U.S. Provisional Application No. 61 / 781,928, filed on Mar. 14, 2013, which are incorporated by reference in their entirety.BACKGROUND OF THE INVENTION[0002]The present invention is directed to computing systems and methods. These computing systems can be applied to communications networks and the like.[0003]Over the last few decades, the use of communication networks exploded. In the early days Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth fo...

Claims

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Application Information

Patent Timeline
21 Apr 2016
Publication
US20160110136A1
IPC
G06F3/06
CPC
G06F3/0659; G06F3/0613; G06F3/0635; G06F3/067; G06F3/0658; G06F13/4022; Y02D10/00; G06F3/0688
Inventors
SAXENA, NIRMAL RAJ; KRISHNAN, SREENIVAS