Multi-hierarchy FPGA

Abstract

The invention discloses a multi-level FPGA, which relates to an integrated circuit technology. The invention comprises a configurable logical block CLB, an interconnection resource and an input-output block IOB, wherein, the interconnection resource comprises a channel, a switch block SB and a connecting block CB, and the CLB is connected with the channel by the connecting block CB; the multi-level FPGA is characterized in that the FPGA comprises at least three layers; each layer comprises a plurality of modules, each module comprises a plurality of arithmetic units, and the arithmetic units and the modules are connected by the interconnection resource; the modules at lower layers constitute the arithmetic units of the modules at higher layers; the passage width between the modules at thelower layers is greater than the passage width between the modules at the higher layers; and the module at the lowest layer is the CLB. The beneficial effects of the FPGA are as follows: the FPGA improves the utilization efficiency of the interconnection resource, and is provided with better delay characteristics compared with the prior art, and the FPGA is more beneficial to the high integrationand miniaturization of the chip.

Description

technical field [0001] The present invention relates to integrated circuits. Background technique [0002] The traditional island-style (isolated island type) FPGA is composed of three components: Configurable Logic Block (CLB), Routing Resource (Route Resource, RRS) and Input / Output Block (I / O Block, IOB). Routing resources include a switch block (Switch Block, SB) and a connection block (Connection Block, CB). Figure 1 is a simplified structure diagram of an isolated island FPGA. CLBs and SBs are arranged symmetrically in arrays. This highly symmetrical structure greatly facilitates software writing, but there are still major problems in the following two aspects: isolated islands The high symmetry of the FPGA structure determines that its chip routing resources cannot be fully used; the routing delay is relatively large. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a multi-level FPGA, which can make full ...

AI Technical Summary

Problems solved by technology

Figure 1 is a simplified structure diagram of an isolated island FPGA. CLBs and SBs are arranged symmetrically in arrays. This highly symmetrical structure greatly facilitates software writing, but there are still major problems in the following two aspects: isolated islands The high symmetry of the FPGA structure determines that its chip routing resources cannot be fully used; the routing delay is large

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