Hierarchical buffer zone management system and method

Abstract

The invention provides a graded buffer management system, which comprises a chip and an external memory, wherein, the external memory comprises an external free buffer queue, the chip comprises an external free buffer queue control module, a control logic module and an internal free buffer queue which is used for storing RAM space of partial buffer addresses, wherein, the priority level of storing the buffer addresses of the internal free buffer queue is higher than that of the external free buffer queue; and the chip also comprises an internal free buffer queue control module which is used for controlling the dequeuing and enqueuing of the internal free buffer queue and for maintaining the pointer of the internal free buffer queue. Besides, the invention provides a graded buffer managingmethod, and therefore, when the flow rate of in and out chips is steady, reading and writing access to the external memory is not needed, thus greatly increasing the efficiency of a buffer manager and increasing the bandwidth utilization of the external memory.

Description

technical field [0001] The invention relates to the field of high-speed data exchange, more specifically, to a hierarchical buffer management system and method for managing large-capacity data storage such as SDRAM, DDR, and DDR2. The memory is divided into many small fragments (called buffers) to store data packets that need to be buffered during data exchange. The application and release of these fragments is managed by the buffer management system. Background technique [0002] In data communication networks, data traffic is very large. These data flows complete the intercommunication between the source port and the destination port at the data exchange point (such as a switch, router, etc.). At each data exchange point, data must be exchanged from a source port to a destination port in a prompt and efficient manner. Data transmitted on the network is usually transmitted in fixed-size packets or data frames with a limited length. Usually, after packets (or data frames...

AI Technical Summary

Problems solved by technology

The efficiency of the buffer manager suffers as external memory typically exhibits significant latency

At the same time, since the buffer manager cannot monopolize an external memory, every read and write to the external memory will also affect the access of other modules in the chip to the external memory, thus affecting the efficiency of other modules

And because the access length of the buffer manager to the external memory is very short (for the external memory is SDRAM or DDR SDRAM, usually 1 is enough, and the requirement for the number of Buffers will not exceed 2^32), this is still Affects the bandwidth utilization of the entire external memory

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