Evaluation method for decoupling capacitor on ASIC sheet based on chain circuit
A technology of chained circuits and capacitors, applied in CAD circuit design, calculation, electrical digital data processing, etc., can solve problems affecting circuits, unstable power supply voltage, etc.
Active Publication Date: 2010-09-08
SOUTHEAST UNIV
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When a circuit reverses and draws a certain amount of current from the power bus, it will cause a certain voltage drop on the power network bus, and this voltage drop will affect the circuits that share the power bus in the chip, making the power supply voltage unstable
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The invention discloses a method for estimating the decoupling capacitors on a chip of an ASIC based on a chain circuit, and belongs to the field of estimation of the decoupling capacitors in inhibition of mains voltage fluctuation. The method comprises: firstly, adopting Star-RCXT to extract parasitic parameters of the ASIC after wiring, and using Perl to analyze the SPF file format and includedinformation for the modeling of the chain circuit; secondly, using an Euler formula to realize the equivalence of the capacitors, and compressing the circuit by a Y-delta conversion method; thirdly, solving the voltage and the current of various nodes of a compressor circuit, and restoring the solving of the chain circuit; and fourthly, adopting integral idea to obtain the number of decoupling capacitors required to be added according to the principle that the voltage fluctuation of the nodes cannot exceed 10 percent of the mains voltage. The method estimates the number of the decoupling capacitors on a chip required to be added between power ground wires, makes the amplitude of mains fluctuation not exceed 10 percent of the mains voltage, and effectively solves the problem of voltage drop of a power network.
Description
technical field The invention relates to a method for estimating decoupling capacitance on an ASIC chip based on a chain circuit in the technical field of suppressing power supply voltage fluctuations. Background technique Studies have shown that the power fluctuation amplitude of the power ground network cannot exceed 10% of the power supply voltage, otherwise it will cause the transmission delay and level of the data signal to be unpredictable, and the synchronous switching noise generated at the same time will bring electromagnetic interference to other signals and reduce the chip's performance. electromagnetic compatibility. Adding an on-chip decoupling capacitor between the power supply and ground can effectively solve this problem. When the circuit is turned over, it will first draw charge from the adjacent decoupling capacitor instead of the power bus. Charging in the power network, so it can suppress the fluctuation of power supply voltage and reduce the synchronou...
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IPC IPC(8): G06F17/50
CPCG06F2217/78G06F17/5063G06F30/36G06F2119/06
Inventor 刘新宁邵金梓杨军时龙兴
Owner SOUTHEAST UNIV
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