Multiprocessor system with hardware semaphore module and realization method thereof

A multi-processor system and hardware signal technology, applied in the field of synchronization and scheduling constraints, mutual exclusion, to achieve the effect of low complexity, reduced complexity, and mutual exclusion of flexible system resources

Inactive Publication Date: 2009-09-30
北京中科银河芯科技有限公司
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0014] In view of this, the main purpose of the present invention is to provide a multiprocessor system with a hardware semap

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  • Multiprocessor system with hardware semaphore module and realization method thereof
  • Multiprocessor system with hardware semaphore module and realization method thereof

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Embodiment Construction

[0045] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0046] In the hardware circuit for realizing the semaphore required by the critical section proposed by the present invention, each semaphore unit in the hardware semaphore module corresponds to one or more shared resources of the multiprocessor system. Each semaphore unit can be accessed by multiple or all processors.

[0047]When the processor performs a read operation on the semaphore module, the semaphore module parses the address corresponding to the read operation, and the semaphore module completes the process of a specific semaphore equivalent to the "read-modify-write" atomic operation, and at the same time, according to the current state of the semaphore Modify the internal state of the semaphore unit and return...

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Abstract

The invention discloses a multiprocessor system with a hardware semaphore module. The system at least comprises a plurality of processors, a hardware semaphore module and a plurality of shared resources; the processors are mutually connected with the hardware semaphore module in a certain interconnection manner and are connected to the shared resources so as to realize the access to the shared resources. The invention also discloses a realization method of the hardware semaphore of the multiprocessor, and the method comprises the following steps: after a processor fails to apply for the hardware semaphore, various subsequent processing methods are provided; and after the subsequent processing to the processor is authorized, the processor can be rapidly waken-up to jump out of a low power consumption mode. The invention can effectively realize the mutual exclusion and the dispatching constraint of the multiprocessor, simplify the programming work of the multiprocessor is combined with the power consumption control of the processor core simultaneously and can realize the design of low power consumption of the system. Compared with other methods, the method is simple and easy for use, is low in complexity and can be conveniently integrated to the designing process of the system.

Description

technical field [0001] The invention relates to the field of multiprocessor systems, in particular to a multiprocessor system with a hardware semaphore module, and a mutual exclusion, synchronization and scheduling constraint method when the multiprocessor system utilizes the hardware semaphore to realize shared system resources. Background technique [0002] Multiprocessor systems, including on-chip multiprocessor systems, where different processors can concurrently access shared resources of the system. A key interaction between hardware and software is in the support of synchronous operations. Synchronous operations include mutexes, point-to-point events, and global events. Different multiprocessor systems provide corresponding hardware primitives to support these synchronization operations. Hardware support has the advantages of speed and efficiency, while software implementation has advantages in flexibility and adaptability to different situations. [0003] When an ...

Claims

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Application Information

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IPC IPC(8): G06F9/46
Inventor 刘建陈杰岳培培
Owner 北京中科银河芯科技有限公司
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