Semiconductor device and method for fabricating the same

Abstract

The present invention discloses a semiconductor device and a mthod for fabricating the same. The method for fabricating a semiconductor device includes forming a metal word line additionally over a vertical transistor to obtain a multi-layered structure, thereby preventing degradation of the operating speed of the semiconductor device by preventing an increase of resistance of a damascene word line that connects a surrounding gate of a vertical transistor. As a result, the yield and reliability of the semiconductor device can be improved.

Description

technical field

[0001] The present invention relates to a semiconductor device, and more particularly, to a structure and a manufacturing method of a semiconductor device for preventing a decrease in the operating speed of the semiconductor device. Background technique

[0002] Semiconductor devices such as DRAM need to accommodate a large number of transistors in a limited area to increase integration. Therefore, a vertical transistor has been proposed for use as an element that typically has a 4F 2 Components included in a memory cell with a higher area of ​​integration. Vertical transistors have a wrap-around gate structure surrounding a vertical channel.

[0003] For an area of ​​4F 2 A surrounding gate is formed in the region of the channel, and the channel region is selectively etched isotropically, so that the channel region is formed thinner than the source / drain region, thereby obtaining good device characteristics. Therefore, vertical transistors can effectivel...

Examples

Embodiment Construction

[0026] Figure 4 is a view showing a semiconductor device according to one embodiment of the present invention.

[0027] Figure 4 The semiconductor device includes a first word line 155 and a second word line 190, the first word line 155 is configured to electrically connect the surrounding gates of the vertical transistors together, the second word line 190 is arranged in parallel with the first word line above a word line, and is configured to supply a gate voltage to the first word line 155 . The second word line 190 is connected to the first word line 155 , and the first word line 155 is electrically connected to the second word line 190 through the contact plug 180 . The second word line 190 includes a metal line having good conductivity. The second word line 190 receives gate power from the peripheral circuit area, and supplies the gate power to the first word line 155 .

[0028] As shown, the gate voltages from the peripheral circuit regions are not applied directly ...

technical field

[0001] The present invention relates to a semiconductor device, and more particularly, to a structure and a manufacturing method of a semiconductor device for preventing a decrease in the operating speed of the semiconductor device. Background technique

[0002] Semiconductor devices such as DRAM need to accommodate a large number of transistors in a limited area to increase integration. Therefore, a vertical transistor has been proposed for use as an element that typically has a 4F 2 Components included in a memory cell with a higher area of ​​integration. Vertical transistors have a wrap-around gate structure surrounding a vertical channel.

[0003] For an area of ​​4F 2 A surrounding gate is formed in the region of the channel, and the channel region is selectively etched isotropically, so that the channel region is formed thinner than the source / drain region, thereby obtaining good device characteristics. Therefore, vertical transistors can effectivel...

Examples

Embodiment Construction

[0026] Figure 4 is a view showing a semiconductor device according to one embodiment of the present invention.

[0027] Figure 4 The semiconductor device includes a first word line 155 and a second word line 190, the first word line 155 is configured to electrically connect the surrounding gates of the vertical transistors together, the second word line 190 is arranged in parallel with the first word line above a word line, and is configured to supply a gate voltage to the first word line 155 . The second word line 190 is connected to the first word line 155 , and the first word line 155 is electrically connected to the second word line 190 through the contact plug 180 . The second word line 190 includes a metal line having good conductivity. The second word line 190 receives gate power from the peripheral circuit area, and supplies the gate power to the first word line 155 .

[0028] As shown, the gate voltages from the peripheral circuit regions are not applied directly ...

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