Test vector coding compression method based on test vector compatibility

Abstract

The invention discloses a test vector coding compression method based on vector compatibility. The method comprises test vector compression and decompression after coding and the following steps: firstly, determining the code of a test vector, and taking vector t1 from a test vector set; completing test vector grouping and test vector group coding by combining with a vector most compatible with t1 and ensuring the increase of overall compression ratio; and during the decoding, shifting the code to a tested circuit for storage and repeating the decoding of the code till restoring the vector set before compression. The test vector coding compression method has the advantages that the method realizes grouping of the test vector set according to the relation of maximal compatibility and completes combined coding of vectors in a test vector group; the method marks an incompatible position by a mark code to substantially reduce bits required during marking by address information; moreover, both ends of the code are respectively inserted with group head information and a group division code; and during the decoding, the code of the test vector group is shifted to the tested circuit for storage so as to be reused, thereby greatly reducing the bandwidth of a testing machine and the tested circuit.

Description

technical field [0001] The invention relates to integrated circuit testing technology, in particular to a test vector coding and compression method based on test vector compatibility. Background technique [0002] With the advancement of chip manufacturing technology and the emergence of new design methods, especially the transition to SOC design methods, a large number of IP (Intellectual Property) cores are combined to form a system-on-chip (SOC, System-On-Chip). As a result, the complexity of the chip increases linearly. The test data of each IP core is generally very large (in order to achieve a high error coverage), the test time becomes lengthy, and the amount of test data becomes extremely large, which makes the test of a single SOC. The test vectors are beyond the allowable range of the test equipment performance, and the test cost rises sharply. Test cost has become a major component of chip cost, and how to reduce test cost and then chip cost has become a growing ...

AI Technical Summary

Problems solved by technology

LFSR has a great advantage in compressing a test set with a large number of irrelevant bits, and is not suitable for determining the number of bits too much

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