Wafer level fan-out chip packaging structure

A chip packaging structure, wafer-level technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of low packaging cost, reduce packaging costs, and solve the effect of chip displacement

Active Publication Date: 2009-12-16
JIANGYIN CHANGDIAN ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The object of the present invention is to overcome the above disadvantages, and provide a wafer-level fan-out chip packaging structur

Method used

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  • Wafer level fan-out chip packaging structure
  • Wafer level fan-out chip packaging structure
  • Wafer level fan-out chip packaging structure

Examples

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[0019] See figure 1 , The wafer-level fan-out (Fanout) chip packaging structure of the present invention includes a thin-film dielectric layer I 101, the thin-film dielectric layer I 101 is formed with a photolithographic pattern opening I 1011, and the pattern opening I 1011 and the thin-film dielectric layer The surface of the I 101 is provided with a metal electrode 102 connected to the substrate end and a rewiring metal trace 103. The surface of the metal electrode 102 connected to the substrate end, the surface of the rewiring metal trace 103 and the surface of the thin film dielectric layer I 101 are covered with The thin film dielectric layer II104 has a photolithography pattern opening II 1041 formed on the thin film dielectric layer II 104, and the photolithography pattern opening II 1041 is provided with a metal electrode 105 connected to the chip end, which will carry the IC chip 106, The chip of the metal pillar / metal bump 107 and the solder 108 is flip-chip mounted o...

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PUM

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Abstract

The invention relates to a wafer level fan-out chip packaging structure, comprising a film dielectric layer I (101), a photoetching pattern opening I (1011) is formed on the film dielectric layer I (101), a metal electrode (102) and a re-wiring metal routing wire (103) which are connected with a base plate end are arranged on the photoetching pattern opening and the surface of the film dielectric layer I (101), a photoetching pattern opening I (1011) is formed on the film dielectric layer I, a film dielectric layer II (104) is covered on the surface of the metal electrode, the surface of the re-wiring metal routing wire, and the surface of the film dielectric layer I which are connected with the base plate end, and a photoetching pattern opening II (1041) is formed on the film dielectric layer II; a metal electrode (105) connected with a chip end is arranged on the photoetching pattern opening II, a chip (106), a metal column/metal salient point (107) and a welding flux are arranged on the metal electrode connected with the base plate end in an inverting way, so as to form a wafer with an inverted chip, packaging material (109) is injected on the surface of the wafer, and a welding ball salient point (110) is arranged on the metal electrode (102) connected with the base plate end. The packaging is low, has a carrying function and can well solve the problem that the chip is shifted in the technological process.

Description

(1) Technical field [0001] The invention relates to a chip packaging structure and a packaging method thereof. It belongs to the technical field of semiconductor chip packaging. (2) Background technology [0002] In the current semiconductor industry, electronic packaging has become an important aspect of industry development. With the development of packaging technology for decades, the traditional peripheral wiring low-pin-count packaging form is increasingly unable to meet the current high-density and small-size packaging requirements. Perimeter routing to area array routing provides a complete solution. Its advantages are: [0003] The number of pins per unit chip area has increased. [0004] Compared with the traditional wire bonding structure, the ball grid array structure shortens the distance between the chip circuit and the substrate, increases the transmission speed of electrical signals, and improves the chip function. [0005] Due to the limitations of the s...

Claims

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Application Information

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IPC IPC(8): H01L23/485H01L23/48H01L23/13
CPCH01L2224/16225H01L2924/15174H01L2924/15311
Inventor 张黎赖志明陈栋陈锦辉曹凯
Owner JIANGYIN CHANGDIAN ADVANCED PACKAGING
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