The invention relates to a wafer level fan-out chip packaging structure, comprising a film dielectric layer I (101), a photoetching pattern opening I (1011) is formed on the film dielectric layer I (101), a metal electrode (102) and a re-wiring metal routing wire (103) which are connected with a base plate end are arranged on the photoetching pattern opening and the surface of the film dielectric layer I (101), a photoetching pattern opening I (1011) is formed on the film dielectric layer I, a film dielectric layer II (104) is covered on the surface of the metal electrode, the surface of the re-wiring metal routing wire, and the surface of the film dielectric layer I which are connected with the base plate end, and a photoetching pattern opening II (1041) is formed on the film dielectric layer II; a metal electrode (105) connected with a chip end is arranged on the photoetching pattern opening II, a chip (106), a metal column/metal salient point (107) and a welding flux are arranged on the metal electrode connected with the base plate end in an inverting way, so as to form a wafer with an inverted chip, packaging material (109) is injected on the surface of the wafer, and a welding ball salient point (110) is arranged on the metal electrode (102) connected with the base plate end. The packaging is low, has a carrying function and can well solve the problem that the chip is shifted in the technological process.