Wafer level fan-out chip packaging method

Abstract

The invention relates to a wafer level fan-out chip packaging method, comprising the following technological processes: a stripping foil and a film dielectric layer I are sequentially covered on the surface of the wafer of a carrier, a photoetching pattern opening I is formed on the film dielectric layer I; a metal electrode and a re-wiring metal routing wire which are connected with a base plate end are arranged on the photoetching pattern opening and the surface thereof, a film dielectric layer II is covered on the surface of the metal electrode, the surface of the re-wiring metal routing wire, and the surface of the film dielectric layer I which are connected with the base plate end, and a photoetching pattern opening II is formed on the film dielectric layer II; a metal electrode connected with a chip end is arranged on the photoetching pattern opening II, after a chip is arranged on the metal electrode connected with the chip end in an inverting way, the injection molding of packaging material and solidification are carried out, so as to form a packaging body with plastic-packaging material; the wafer of the carrier and the stripping foil are separated from the packaging body with plastic-packaging material, so as to form a plastic-packaging wafer; a welding sphere back returns to form a welding ball salient point; cutting is carried out by uniwafers for forming the final structure of the fan-out chip. The method has low cost and a carrying function, and can well solve the problem that the chip is shifted in the technological process.

Description

(1) Technical field [0001] The invention relates to a chip packaging structure and a packaging method thereof. It belongs to the technical field of semiconductor chip packaging. (2) Background technology [0002] In the current semiconductor industry, electronic packaging has become an important aspect of industry development. With the development of packaging technology for decades, the traditional peripheral wiring low-pin-count packaging form is increasingly unable to meet the current high-density and small-size packaging requirements. Perimeter routing to area array routing provides a complete solution. Its advantages are: [0003] The number of pins per unit chip area has increased. [0004] Compared with the traditional wire bonding structure, the ball grid array structure shortens the distance between the chip circuit and the substrate, increases the transmission speed of electrical signals, and improves the chip function. [0005] Due to the limitations of the s...

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Problems solved by technology

[0009] The purpose of the present invention is to overcome the above disadvantages, and provide a wafer-level fan-out chip packaging method and packaging method with low packaging cost, tape carrier function, and a good solution to the problem of chip displacement in the process

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