Multipath E1 error code tester and multipath E1 error code testing method

Abstract

The invention discloses a multipath E1 error code tester and a multipath E1 error code testing method. The structure of the tester comprises a plurality of E1 signal interfaces, a TVS tube, a transformer chip, an E1 interface chip, an error code detecting module, a local regulating and testing module and a local regulating and testing interface, wherein, the local regulating and testing interfaceis connected with an external PC for receiving monitoring information sent from outside and reporting error code testing data and warning event transmitted from the local regulating and testing module; the error code testing data comprise error code number recorded by the error code testing module. The multipath E1 error code tester of the invention can be connected with an upper computer via a manner of network interconnection and is intensively managed by the upper computer. The invention also can simultaneously perform the multipath E1 error code test.

Description

technical field [0001] The invention relates to E1 error code testing technology, in particular to a multi-channel E1 error code tester and a multi-channel E1 error code test method. Background technique [0002] The principle of the E1 bit error tester is: the E1 bit error tester itself generates a pseudo-random sequence signal, and then sends it to the E1 device to be tested. Send it to the E1 BER tester, and finally the E1 BER tester compares whether the pseudo-random sequence signal generated by itself is consistent with the E1 signal received from the E1 device, and then reports the test result to the user. [0003] The traditional E1 bit error tester has a structure such as figure 1 As shown, it includes E1 signal interface, TVS tube, transformer chip, E1 interface chip, FPGA and monitoring module that are electrically connected in sequence. The monitoring module is also connected to the LCD panel and the key panel respectively to realize visualization and man-machine...

AI Technical Summary

Problems solved by technology

[0006] 1. A single E1 bit error tester can only detect the bit error of one E1 signal. When the user needs to test multiple E1 devices or test the bit error of multiple E1 signals of a single E1 device, it is necessary to test each E1 one by one. Signal, or equipped with a corresponding number of E1 bit error testers to test one by one, the equipment cost is high;

[0007] 2. When multiple E1 BER testers are used for multi-channel BER testing, testers need to operate E1 BER testers one by one, and at the same time set the test parameters of E1 BER testers one by one, such as test time, start-up test, etc. After the test is over, the testers need to manually collect the error test data or print the test report one by one through the LCD panel of the tester, and input the collected error test data into the computer for summary analysis or make statistical reports, which cannot satisfy users. Customize functions according to requirements, such as customizing the printing report format, etc., which lacks scalability; moreover, the test efficiency is low and the cost of human resources is large;

[0008] 3. Since the traditional E1 bit error tester only provides external buttons for users to operate, and the E1 bit error tester itself can only provide a limited number of buttons, which reduces the operability of the tester; at the same time, each The tester must be equipped with a liquid crystal panel, which greatly increases the manufacturing cost of the equipment;

[0009] 4. Since it cannot be connected to the LAN through the Ethernet port, centralized management cannot be realized; testers are required to perform manual control tests on each device, increasing the dependence of tests on recorders;

[0010] 5. The traditional test method requires testers to collect and record test data from each device, and then input it into the computer for statistical analysis, which also reduces the reliability of test data and increases the workload of statistical analysis

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