Method and device for preventing CPU local bus from suspension

Abstract

The invention discloses a method and a device for preventing a CPU local bus from suspension. The method comprises a step of constructing a TA signal in accordance with a CPU time sequence and transmitting the TA signal to a CPU when a logic processing unit of slave equipment determines that the slave equipment is time-out and does not transmit the TA signal. The device comprises the CPU, the slave equipment and the logic processing unit of the slave equipment which are connected sequentially, wherein the logic processing unit of the slave equipment is used for constructing the TA signal in accordance with the CPU time sequence and transmitting the TA signal to the CPU when determining that the slave equipment is time-out and does not transmit the TA signal. The method and the device are applicable to application of providing the TA signal by using the slave equipment to prevent the CPU local bus from suspension, and can position failure equipment to avoid failure diffusion and improve system stability.

Description

technical field [0001] The invention relates to the field of computer communication, in particular to a method and a device for preventing a CPU local bus (Local Bus) from hanging up in a computer communication hardware platform. Background technique [0002] In the computer communication hardware platform, when the CPU (master device) accesses the peripheral device (slave device) through the microprocessor interface, in order to ensure the normal communication and coordination between the master and slave devices, there are generally two transmission response methods between the master and slave devices: [0003] (1) The CPU generates the TA signal to end the read or write operation with the slave device. When the CPU reads and writes the slave device through the microprocessor interface, a fixed waiting period is set by the CPU internal register. When the fixed waiting period comes during each read and write operation, the CPU generates a TA signal to end the operation. r...

AI Technical Summary

Problems solved by technology

Under normal circumstances, the slave device will normally output the TA signal, but when the slave device is busy processing internal interrupts or DMA (direct memory access mode) scheduling is not timely, or the slave device fails, the CPU will read the slave device once. The case where the slave device cannot output the TA signal within the maximum time of write operation access

This will cause the local bus of the CPU to hang up, causing the system to fail to work normally.

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