Burst clock utilizing phase selecting technology and data recovery circuit

Abstract

The invention relates to a burst clock utilizing phase selecting technology and a data recovery circuit, comprising a phase-locked loop circuit, an over-sampling phase selecting circuit and a delay locking loop circuit, wherein the phase-locked loop circuit is used for providing multiple groups of fixed clock signals, and each clock signal has a clock phase. The over-sampling phase picking circuitis coupled to the phase-locked loop circuit and is used for detecting the data edge of the received date signals by utilizing the clock signals and select a to-be-locked clock phase according to theposition of the data edge. The delay locking loop circuit is coupled to the phase-locked loop circuit and the over-sampling phase selecting circuit and is used for comparing the data phase of the datasignal with the to-be-locked clock phase, thereby controlling the data phase of the data signal to be delayed by a delay time until the data phase is locked to the clock phase.

Description

technical field [0001] The invention relates to a burst-mode (Burst-mode, BM) clock and data recovery circuit using phase selection technology. Background technique [0002] With the rise of broadband applications, people's demand for bandwidth is getting higher and higher, and optical fiber can provide ultra-large bandwidth, good and stable transmission quality, and is the ultimate solution to broadband requirements. At present, the most popular method of realizing fiber-to-home is a low-cost passive optical network (Passive Optical Network, PON). [0003] figure 1 A schematic diagram of a conventional passive optical network is shown. Please refer to figure 1 , the passive optical network 100 is composed of an optical line terminal (Optical Line Termination, OLT) 110, an optical distribution network (Optical Distribution Network, ODN) 120, and a plurality of optical network units (Optical Network Unit, ONU) 130. The optical line terminal 110 is mainly placed at the cen...

AI Technical Summary

Problems solved by technology

However, such an architecture still lacks the ability to eliminate phase errors in the circuit. When the data jitter increases, the sampled phase may be wrong, which will eventually cause data reply errors

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