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Bus monitoring method and apparatus based on AHB bus structure

A technology of monitoring device and bus structure, which is applied in the direction of instruments, electrical digital data processing, memory systems, etc., can solve the problems that the bus monitoring technology has not yet had relatively mature implementation methods and examples, and achieve the goal of avoiding deadlock and ensuring consistency Effect

Active Publication Date: 2012-07-25
BEIJING PKUNITY MICROSYST TECH
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AI Technical Summary

Problems solved by technology

However, the existing SoC based on the AHB bus structure mainly adopts strategies such as software flushing and setting the address space not to be cached by the Cache, especially for the single-processor bus structure, there is no mature implementation method and example of bus monitoring technology

Method used

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  • Bus monitoring method and apparatus based on AHB bus structure
  • Bus monitoring method and apparatus based on AHB bus structure
  • Bus monitoring method and apparatus based on AHB bus structure

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Embodiment Construction

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0042]The present invention is aimed at a single processor system, only the Cache in the processor keeps a copy of the main memory data, so in order to ensure the consistency of the Cache, it is only necessary to monitor the request of the bus master to access the main memory, and for the request of the processor to access the main memory No monitoring is required. The essence of the present invention is that a bus monitoring device is added between the storage control unit and the bus to filter memory access requests issued by the bus master. If the memory access request may affect the Cache consistency, the processor is notified to carry out the Cache consistency processing, and after the consistency processing ends, the bus monitoring device is notified to allow the request to access the storage control unit; if the memory access r...

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Abstract

The invention discloses a bus monitoring apparatus and method based on AHB bus structure, which is used for single-processor system in AHB bus structure. The bus monitoring apparatus is disposed between the memory control parts and the AHB bus, used for filtering access and storage requests sent out by main apparatus of bus. When the bus monitoring device monitors the access and storage request affecting the consistency of the Cache, the processor is notified to perform a Cache consistence processing, prevent the access and storage requests causing monitoring hit from getting access to the memory control part, until the Cache consistence processing is ended.

Description

technical field [0001] The present invention relates to a bus monitoring technology for ensuring cache (Cache) consistency in a system chip (System-on-Chip, hereinafter referred to as SoC), in particular to a single-processor SoC chip based on an AHB (Advanced High-performance Bus) bus structure A bus monitoring method and device. Background technique [0002] The advancement of semiconductor technology and the development of integrated circuit design technology have made it possible to integrate the functional components of the entire system on a single chip. At present, SoC has become the mainstream technology of today's integrated circuits. In SoC structure design, the method of ensuring cache coherence has a certain influence on the performance of the whole system. [0003] In the processor, the Cache stores a copy of the data in the main memory. If the master device on the bus accesses the main memory, the data in the Cache may be inconsistent with the main memory, re...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F13/40G06F12/0831
Inventor 程旭陆俊林庞九凤佟冬施云峰
Owner BEIJING PKUNITY MICROSYST TECH
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