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Bytecode caching device and accessing method for real-time Java processor

A high-speed cache and bytecode technology, which is applied to the architecture with a single central processing unit, machine execution device, general-purpose stored program computer, etc., can solve the problems of low utilization rate and long waiting time of the processor, and achieve the reduction of CPU pause effect

Active Publication Date: 2012-09-05
JIANGSU LANCHAUNG INFORMATION TECH SERVICESCO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The advantage is that the execution time is easy to predict statically, but the problem is that the utilization rate of the loaded method is low, and the processor waits for a long time when the method is called and returned.

Method used

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  • Bytecode caching device and accessing method for real-time Java processor
  • Bytecode caching device and accessing method for real-time Java processor
  • Bytecode caching device and accessing method for real-time Java processor

Examples

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Embodiment Construction

[0032] Such as figure 1 As shown, the device proposed by the present invention includes a bytecode counter 1, a cache read address multiplexer 3, a cache write address multiplexer 4, a cache read address register 5, and a cache write address register 6 , cache read address adder 7 , cache write address adder 8 , bytecode readable comparator 9 , bytecode writable comparator 10 , main memory 13 , cache memory 14 and bytecode register 15 .

[0033] Among them, the bytecode counter 1 is used to save the address of the bytecode to be executed with the byte as the addressing unit, and the byte as the addressing minimum unit, which is adjusted by the decoding segment of the CPU according to the actual length of the current bytecode . The width of the bytecode counter 1 is determined by the address width of the main memory 13 . The address of the bytecode counter 1 is sent to the cache write address multiplexer 4 after the address alignment operation 2 .

[0034] figure 2 It is a...

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Abstract

The invention relates to a bytecode caching device and an accessing method for a real-time Java processor, and belongs to the field of computers. The device comprises a bytecode counter, a caching read address multiplexer, a caching write address multiplexer, a caching read address register, a caching write address register, a caching read address summator, a caching write address summator, a bytecode readable comparator, a bytecode writable comparator, a main memory, a cache and a bytecode register. The device utilizes the characteristic that Java bytecodes have unequal length and mostly have less than 4 bytes, takes four bytes each time and uses up the bytes for several times so as to generate the prefetching time. The device has an automatic instruction prefetching mechanism, thereby decreasing the CPU pauses caused by fetching the instruction, and also determining the positions of missed bytecode to statically forecast the access time of the bytecodes. The performance of the Java processor can be greatly improved while the predictable program implementation is ensured.

Description

(1) Technical field [0001] The invention relates to a cache memory mechanism of a Java processor in the computer field, in particular to a bytecode (instruction) cache device and an access method for a real-time Java processor. (2) Background technology [0002] In order to match the access speed of the memory with the execution speed of the CPU as much as possible, the current computer system generally meets the various requirements of access speed, storage capacity and manufacturing cost through a multi-level memory structure. Usually, the memory with fast access speed but high manufacturing cost is placed closer to the CPU with a smaller storage capacity, and it stores a data subset of the larger memory farther away from the CPU. According to the principle of program locality, in most cases, the CPU will access the required data in the high-speed memory close to it, and only a few cases need to access the far memory, and copy a batch of data to the high-speed memory. In ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F15/78
Inventor 柴志雷涂时亮吴小俊须文波孙俊叶新栋
Owner JIANGSU LANCHAUNG INFORMATION TECH SERVICESCO LTD
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