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Method for multiplexing IO units in stream processor

A stream processor and multiplexing processing technology, applied in the direction of machine execution device, concurrent instruction execution, etc., can solve the problems of increased design area and delay, inconvenient programming for programmers, no longer able to provide support, etc., to reduce the number of selectors , the effect of reducing the number of IO units and reducing the instruction field

Inactive Publication Date: 2012-05-09
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A large number of IO units will make the size of the selector in the interconnection switch in the cluster become very large, and the number of selectors will increase as the number of IO units increases, which will lead to a sharp increase in design area and delay
In addition, each IO unit requires a dedicated decoding unit and execution unit, and a large number of IO units will also consume a certain amount of hardware logic
[0008] (3) Most importantly, each IO unit can only execute one stream, which also limits the number of streams supported by the processor. Once the data streams that need to be transmitted at the same time exceed the number of IO units, the system will no longer be able to provide support, requiring programmers Adjust the program to bring inconvenience to the programmer

Method used

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  • Method for multiplexing IO units in stream processor
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  • Method for multiplexing IO units in stream processor

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Embodiment Construction

[0044] figure 1 It is the logical structure diagram of the current Imagine series stream processor. The stream processor is composed of a main processor, DRAM memory, storage controller, stream controller, microcontroller, stream register file SRF and multiple computing clusters, and all components are connected by an on-chip general bus. All calculation operations in the stream processor are completed by the calculation cluster, and the input data stream, output data stream and intermediate data related to the calculation are all stored in the stream register file SRF to ensure that the data can be recycled inside the processor without external DRAM memory is accessed. The VLIW code generated by compiling the core program is stored in the microcode memory of the microcontroller. When the core program starts, the microcontroller broadcasts the VLIW code to each operation cluster one by one, and controls each operation cluster to execute in SIMD mode.

[0045] figure 2 yes ...

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Abstract

The invention discloses a method for multiplexing IO units in a stream processor, which aims to solve the technical problems of overcoming the limitation that one IO unit can only execute one stream in the design of the stream processor, achieving the extended support for a large amount of input and output streams by a small amount of IO units, and reducing the hardware expense. The technical scheme is that the method comprises the following steps: modifying a compiler, adding an IO unit multiplexing processing module in the compiler, distributing a stream identifier to each stream, and scheduling IO operations to the IO units appointed by the stream identifier for execution; improving a hardware structure of an operational cluster in the stream processor, and adding K multipath selectorsbetween the IO units and a stream buffer; and decoding the stream identifier by the IO units, using the decoding result as an arbitration signal, and arbitrating the visit to the streams by each multipath selector according to the arbitration signal so as to achieve the input and the output of the streams. By using the method, the number of the input and output streams is not limited by the number of the IO units any more, the number of the IO units is greatly reduced, and the hardware expense is small.

Description

technical field [0001] The invention relates to a design method of a flow processor, in particular to an IO unit multiplexing method in the design of the flow processor. Background technique [0002] The stream processor is a typical representative of a new generation of intensive computing-oriented high-performance microprocessors, specifically for stream applications. Streaming applications are computationally intensive: Compared with traditional desktop applications, streaming applications perform a large number of arithmetic operations on each data fetched from memory. [0003] The stream processor is composed of a scalar core, a DRAM controller, a storage controller, a stream controller, a microcontroller, a stream register file SRF (Stream Register File), and multiple computing clusters, and all components are connected through an on-chip general bus. The main idea of ​​stream processing is to divide the application program into computing core functions (kernels), gen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
Inventor 管茂林荀长庆张春元杨乾明何义文梅伍楠任巨吴伟柴俊苏华友全巍
Owner NAT UNIV OF DEFENSE TECH
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