Layout structure for promoting pixel defection detectivity of thin film transistor substrate

Abstract

The invention provides a layout structure for promoting pixel defection detectivity of a thin film transistor substrate, comprising multiseriate first data lines and multi-row first scanning lines; a plurality of pixels are defined by utilizing the multiseriate first data lines and the multi-row first scanning lines; a thin film transistor is formed in each pixel; a gate electrode, the first scanning lines and a common electrode line of the thin film transistor are simultaneously formed by utilizing a first metal layer; a drain electrode, a source electrode and a first data line of the thin film transistor are formed on the thin film transistor by utilizing the second metal layer; the drain electrode of the thin film transistor is connected with a pixel electrode; the common electrode line is arranged adjacent to the first scanning line and the first data line, and is partially covered by the pixel electrode; a virtual data line is positioned between the first scanning line and the common electrode line, and is connected with the pixel electrode, can effectively and rapidly position short circuit of the GC short, and effectively solves the trouble having to be found by human eyes in the prior art.

Description

【Technical field】 [0001] The invention relates to a layout structure for improving the pixel defect detection rate of a thin film transistor substrate, in particular to a thin film transistor substrate layout structure for locating short-circuit defects by using dummy data lines. 【Background technique】 [0002] After the array process (Array process) is completed, an array process test (Array test) is equipped to check whether the thin film transistor meets the requirements. For example, in the Array test, it is checked whether the metal lines (scanning lines, data lines, common electrode wiring) meet the requirements, whether the transistors meet the requirements, and so on. [0003] When the test voltage is input, if there is a short circuit between the data line and the scanning line (source / gate line short, SG short), the screen of the detector will display a "cross" word line, and the intersection point of the cross is the short circuit (defect) , the positioning is ve...

AI Technical Summary

Problems solved by technology

The current method is to locate the place where the lowest voltage appears on the "one" line, and start to find the short circuit with human eyes, which consumes labor costs

The existing technology does not propose an effective solution to GC short

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