Row reading circuit
A technology of reading circuit and sampling circuit, applied in the direction of instruments, static indicators, etc., can solve the problem of large circuit area of the line reading circuit
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no. 1 example
[0017] Please refer to figure 1 , which is a block diagram of an image sensing device applying the row readout circuit according to an embodiment of the present invention. The image sensing device 1 includes a pixel array 12, a column decoder (Row Decoder) 14, a row decoder (ColumnDecoder) 16, a timing controller (Timing Controller) 18, a row readout module 20, a bias circuit 22 and an output processor twenty four.
[0018] The pixel array 12 is, for example, a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) pixel array with a size of M×N, which is used to generate a sensing image with a size of M×N pixels, wherein M and N are both larger than The natural number of 1. The pixel array 12 is controlled by the column decoder 14, the row decoder 16, the timing controller 18 and the bias circuit 22, and the sensing image generated by it can pass through the data lines SL1-SLM, the row readout module 20 and the output processor 24 output. ...
no. 2 example
[0034] Please refer to Figure 4 and Figure 5 , Figure 4 A circuit diagram showing a row output circuit according to a second embodiment of the present invention, Figure 5 painted Figure 4 The relevant signal waveform diagram of the line output circuit. Different from the first embodiment, the levels at both ends of the sampling capacitors C1 ′ to C4 ′ in the sampling circuits 202 ′ and 204 ′ of this embodiment are provided by the control circuit 206 ′, and the control circuit 206 ′ is also used for the corresponding sampling During the period, the reference voltage Vr4 is provided to the sampling capacitors C1 ′˜C4 ′.
[0035] More specifically, the switches SW5', SW7' and SW9' are respectively turned on in response to the control signals S5', S7' and S9' in the sub-scanning period TS1' to form a short-circuit path to provide the reference voltage Vr4 to the sampling capacitor C1' and One end of C3'. In this way, the sampling capacitors C1' and C3' respectively samp...
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