Digital phase-locked loop device

Abstract

The invention relates to a phase-locked loop device which captures a received universal serial bus differential signal with a frequency signal with the frequency four times higher than the transmission frequency of a universal serial bus, prevents a metastable state caused by the desynchrony of data and the frequency signal from being transmitted to other circuits with a synchronizer, leads a universal serial but controller to produce the frequency signal through a phase-locked loop state machine which comprises a phase detector and the state machine containing four states; and the frequency is locked in the received universal serial bus differential signal, and the data of a transmission end can be accurately received. Through the phase-locked loop state machine containing the four states, the CLKB when the device receives can be more quickly produced, so as to enlarge the frequency tolerance error range of a receiving end. In addition, a two-stage trigger serves as the synchronizer, so that the device can work more stably.

Description

technical field [0001] The present invention relates to a phase-locked loop device, in particular to a phase-locked loop device of a finite state machine with four states. Background technique [0002] The latest Universal Serial Bus specification is based on the USB-IF (USB Implementers Forum) Universal Serial Bus 2.0 specification, which regulates the speed at which Universal Serial Bus transmits data, such as low speed (Low speed) specifies the bandwidth of data It is 1.5 megabits per second (Mb / s), and the error tolerance is 1.5%. %, applicable devices include USB speakers, USB flash drives, etc.; while the high-speed (High speed) bandwidth is 480 megabits per second (Mb / s), which is suitable for data bandwidth requirements taller device. [0003] The transmission of the universal serial bus uses two signal lines D+ and D-, and the change of its potential is used to transfer data. figure 1 It is a block diagram of an existing device controller. When the device is used...

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Problems solved by technology

[0005] For the frequency generator 103, the prior art has used a digital phase-lock-loop (Digital phase-lock-loop), but its disadvantage is that it is too complicated, such as U.S. Patent No. 6,088,811, while another U.S. Patent No. 6,664,859 proposes a more For a simplified mechanism, only a single five-state state machine 301 (State machine), such as Figure 3A As shown, a frequency period of one speed can be generated at a frequency of four times speed. Although a method for effectively reducing complexity is indeed proposed, there is still room for improvement in the speed of the output frequency of the mechanism; , using only one-stage flip-flop (Flip-Flop) as the synchronizer 302 (Synchronizer), so that its structure cannot effectively exclude the first-stage flip-flop from entering a metastable state, which will cause subsequent circuits to be unable to effectively operate

Among them, the reason for the metastable state is that the data changes within the setup time or hold time of the trigger, that is, the Q terminal of the output cannot lock the data, resulting in oscillation or uncertainty level

[0006] For this reason, the inventor of this case has developed a phase-locked loop state machine, especially a phase-locked loop state machine with four states, to improve the current situation that the output frequency delay (latency) is relatively long in the prior art , and further enhance the stability of the system

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