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Semiconductor package substrate with metal bumps

A technology for packaging substrates and substrates, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., and can solve problems such as structural degradation, low fatigue life, and reliability of solder balls

Inactive Publication Date: 2010-07-07
R·阿迪穆拉 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Additionally, solder balls present reliability issues and may degrade structurally
The solder is the material with the lowest fatigue life throughout the package structure

Method used

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  • Semiconductor package substrate with metal bumps
  • Semiconductor package substrate with metal bumps
  • Semiconductor package substrate with metal bumps

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0037] figure 1 A packaging substrate for a microelectronic die prior to attaching the microelectronic die is illustrated according to one embodiment of the present invention. The package substrate 200 shown includes a substrate base 201 and a plurality of conductive bumps 225 formed on the bottom of the substrate base 201 .

[0038] Substrate base 201 may include various layers - for example, top solder mask 215; copper traces formed on bismaleimide-triazine (BT) core layer 205 layer 210; and contact pads 203 formed on the top surface. Other layers may also be included on the substrate base - for example a bottom solder resist opposite the top solder resist, at the bottom of the BT core layer in view of the routing of the conductive bumps 225 to the opposite side of the substrate. Metal wiring layer, etc. Although the layers are shown as one coherent contiguous layer for purposes of illustration, it should be understood that not all layers are contiguous. For example, the...

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Abstract

An apparatus and method of making a package substrate with metal bumps is presented. The package substrate comprises a substrate base and a plurality of metal bumps which are formed on the substrate base. A microelectronic die may thereafter be attached to the package substrate. Also presented is a method for attaching the package substrate to a printed circuit board (PCB).

Description

technical field [0001] Embodiments of the invention relate generally to semiconductor fabrication. More specifically, embodiments of the present invention relate to semiconductor package substrates. Background technique [0002] Package substrates are usually composed of multiple layers and are usually flat. A microelectronic die is attached to the top surface of the package substrate - for example by flip chip technology. Before the die is attached to the packaging substrate, there are no interconnects connecting the packaging substrate to the printed circuit board (PCB). After attaching the microelectronic die to the top layer of the substrate, the entire assembly is connected to the PCB by applying solder bumps on the bottom layer of the substrate and subjected to solder reflow. For example, substrates for MMAP packages (molded matrix array packages) typically have solder bumps applied to the bottom of the substrate after the die is attached. The die-attached package ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/12H01L21/50H05K3/32H05K3/34
CPCH01L2924/15311H01L23/3121H01L2924/01078H05K3/323H01L2924/19043H05K2201/10719H01L2924/01079H01L24/48H01L2224/48091H01L23/49811H01L2224/48227H01L2924/07802H01L2924/181H01L2924/00014H01L2924/00011Y10T29/49144Y10T29/4913H01L2924/00H01L2924/00012H01L2224/45099H01L2224/45015H01L2924/207H01L2924/01005H01L2924/01004H01L2924/01033
Inventor R·阿迪穆拉任明镇
Owner R·阿迪穆拉
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