Floating body cell structure of dynamic random access memory and manufacturing technology thereof

Abstract

The invention discloses a floating body cell structure of a dynamic random access memory and manufacturing technology thereof. The structure comprises a P type semiconductor area on a buried oxide layer (BOX), an N type semiconductor area on the P type semiconductor area and a gate area on the N type semiconductor area. Electric isolation areas are arranged around the N type semiconductor area and the P type semiconductor area. In the invention, isolated floating body gate diodes are employed as the storage nodes. Through tunneling among bands, the state that the electrons are accumulated in the floating body is defined as the first storage state. Through forward bias of PN junctions, the state that the electrons are transmitted from the floating body or holes are injected into the floating body is defied as the second storage state. The two states lead to difference of the forward turn-on voltage of the floating body gate diodes (N+ / P+) and can be sensed through the current intensity. The gate diode (N+ / P+) floating body cell of the memory has high efficiency, low power consumption and high density and has the advantages of simple manufacturing technology, high integration density, low cost, high reliability, etc.

Description

technical field [0001] The invention relates to a memory cell structure and a manufacturing process thereof, in particular to a dynamic random access memory (DRAM) cell structure utilizing a floating body effect (FBE, Floating Body Effect) and a manufacturing process thereof, belonging to the technical field of semiconductor manufacturing. Background technique [0002] With the development of VLSI technology, advanced technology enables people to integrate processors, memory, analog circuits, interface logic and even radio frequency circuits into a large-scale chip to form a so-called system on chip (SoC). As an important part of SoC, embedded memory and other logic circuits are integrated in one chip. At present, the proportion of the total chip area in microprocessors and system chips has exceeded 50%, and as the needs of applications will increase continue to grow. Following Moore's Law, the feature size of CMOS technology will continue to be scaled down to below 40nm, a...

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Problems solved by technology

[0004] This 1T / FB unit structure reduces the unit area, and its unit area size is 4-7F 2 (F refers to the feature size), which greatly improves the integration of memory, but this kind of cell structure will increase the complexity of circuit and logic design, and its leakage current characteristics are also difficult to control

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