Flash memory device with single-poly structure and method for manufacturing the same

Abstract

A flash memory device has a single-poly structure. A method for manufacturing the flash device includes forming an oxide layer over a semiconductor substrate having a P-well region or N-well region. A shallow trench isolation (STI) may be formed in the semiconductor substrate and the oxide layer. A drift region may be formed by injecting a dopant into a part of the P-well region or N-well region. A gate oxide layer and a poly-silicon layer may be formed over the well region, the drift region, and the STI. A control gate pattern may be formed by patterning the gate oxide layer and the poly-silicon layer. A source region and a drain region may be formed on opposite sides of the control gate pattern. A silicon nitride layer may be deposited over the control gate pattern and etching the silicon nitride layer to form a spacer around a sidewall of the control gate pattern. A plurality of insulating layers may be formed over the control gate pattern, and via-patterns may be electrically connected to the source region and the drain region, respectively. A drain electrode and a source electrode may be electrically connected to the via-patterns, respectively.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2006-0085484 filed on Sep. 6, 2006, which application is hereby incorporated by reference. technical field [0002] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a flash memory device with a single polycrystalline structure capable of reducing the cross-sectional area and a manufacturing method thereof. Background technique [0003] A flash memory is a programmable ROM (PROM) capable of electrically rewriting data. Flash memory is an erasable PROM (EPROM) whose storage element includes a single transistor and has a small area, but must be erased with ultraviolet light every time, and an electrically erasable PROM (EPROM) that can electrically erase data, but the storage element includes two transistors and has a large area. In addition to the combination of PROM (EEPROM). The flash memory is a device for performing a program input met...

AI Technical Summary

Problems solved by technology

Also, since the control gates, NMOS and PMOS read transistors, channels or carrier injection regions, etc. are formed in parallel to the substrate surface, there is a limit to cell size reduction

[0009] As a result, the above-mentioned conventional split-gate devices occupy a large area and require electric lines for the respective regions, resulting in a very complex cell structure

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