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esd protection for finfet

A planar and transistor technology, applied in the field of electrostatic discharge protection circuit, can solve the problem of long duration and achieve the effect of reducing the possibility of failure

Active Publication Date: 2011-12-07
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

HBM is usually the smallest voltage amplitude of the three modes, but usually lasts the longest

Method used

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Embodiment Construction

[0015] The manufacture and use of the present invention will be described in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely specific ways to make and use the invention, and do not limit the scope of the invention.

[0016] The invention will be described below with respect to embodiments in a specific context, namely, a circuit for cross-domain protection of FinFETs in a CDM ESD event. However, the present invention can also be applied to other transistor devices and other ESD events without being limited thereto.

[0017] Before the use of FinFETs became common, ESD cross-domain protection of transceiver circuits on semiconductor chips was considered impossible because the active region of the device was large enough to withstand the current generated by an ESD event; ESD protection was only set at...

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Abstract

This invention discloses a ESD protecting method for fin field effect transistor(FinFET) . One embody of this invention is a semiconductor includes: a receiver circuit including fin field effect transistor(FinFET); a transceiver circuit including fin field effect transistor(FinFET); a transmission bus which is linked between the receiver circuit and the transceiver circuit, where both the receiver circuit and the transceiver circuit further include a protective circuit for electrostatic discharge. Said protective circuit for electrostatic discharge includes planar transistor being electrically linked to the planar transistor of the transmission bus. Other embodies of this invention may further include a power clamping electrically connected between the first power bus and the first grounding bus, a power clamping electrically connected between the second power bus and the second grounding bus, or at least two diodes electrically connected between the first grounding bus and the second grounding bus in crosswise mode. In addtion, both the planar transistors of receiver circuit and the transceiver circuit includes the planar PMOS transistor and planar NMOS transistor.

Description

technical field [0001] The present invention relates generally to a circuit for electrostatic discharge (ESD) protection, and more particularly to a circuit for a fin field effect transistor (FinFET) in a semiconductor chip during charge device mode (CDM) discharge. (cross-domain) protected circuit. Background technique [0002] Fin Field Effect Transistors (FinFETs) are more frequently used in semiconductor technology as the size of semiconductor technology decreases. Unfortunately, due to the relatively small channel width of FinFETs, FinFETs are generally more susceptible to device failure caused by electrostatic discharge (ESD) events. Thus, a solution to this problem is needed. [0003] Because of their physical structure, FinFETs are considered three-dimensional transistors. The active regions (drain, channel, and source) of a FinFET protrude from the surface of the semiconductor substrate on which the FinFET sits, much like a rectangular box. Furthermore, the gate...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L23/60H01L21/60
CPCH01L2924/0002
Inventor 李介文娄经雄
Owner TAIWAN SEMICON MFG CO LTD