Reconfigurable transverse summing network structure for supporting fixed and floating points

Abstract

The invention discloses a reconfigurable transverse summing network structure for supporting fixed and floating points, which comprises a floating point index operating part, a floating point mantissa operating / fixed point operating part and a floating point normalization operating part which are connected in turn, wherein the floating point index operating part is used for finishing selection of an index maximum and solution of an index difference, and outputting the obtained index difference to the floating point mantissa operating / fixed point operating part; the floating point mantissa operating / fixed point operating part is used for finishing displacement alignment, data compression and data summation of a floating point mantissa and complement code conversion of a floating point result, finishing lead 0 prediction and judgment required for floating point normalization operation in parallel through the other bypass at the same time, and outputting the obtained processing resultto the floating point normalization operating part; and the floating point normalization operating part is used for finishing normalized displacement of the floating point mantissa and index adjustment. The reconfigurable transverse summing network structure reduces key channel time delay of a multi-input floating point addition, reduces operation resources consumed by fixed point summation, and reduces the power consumption.

Description

technical field [0001] The present invention relates to the technical field of processor design, in particular to a reconfigurable horizontal summation network structure supporting fixed-floating points, aimed at the core computing components of processors in the high-performance field, especially for supporting different types and variable sizes The way multiple input operands are summed in parallel. Background technique [0002] At present, with the continuous development of technology, the high computing-intensive fields represented by modern radar signal processing, satellite image processing, spread spectrum communication, image compression, scientific computing, high-definition television, etc., require more and more signal processing capabilities. come higher. Although the current multi-core parallel architecture has become the main way to solve the bottleneck of computing needs, in the processor, no matter how complex the operation is, it must be completed by the co...

AI Technical Summary

Problems solved by technology

According to the above analysis, it can be found that in parallel multi-input floating-point addition, there are a large number of repetitive processes

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