High efficiency storing method for coding digit of LDPC coder based on FPGA

Abstract

The invention discloses a high efficiency storing method for the coding digit of an LDPC coder based on an FPGA. In the method, the coding digit and external information (or channel information) share one storage block, thereby effectively reducing the requirement of the coder to the quantity of the storage resources; and the coding digit and the external information can be withdrawn when readingthe storage block. Therefore, a check equation computational unit PCU and a check node update unit CNU can share one group of address information, and the PCU does not need additional address generation units; and finally, the design method of a step thinning production line is adopted to realize process units VNU, CNU and PCU, thereby effectively reducing the key path delay of the coder and providing a necessary safeguard to improve the throughput of the LDPC coder. When realizing the method with the FPGA, the invention not only can save a large number of the resources for respectively storing the digit and the logic resources for generating addresses which are needed by the PCU, but also can improve the throughput of the coders.

Description

technical field [0001] The present invention relates to a method for storing decoding codewords of an LDPC decoder, specifically a method for sharing the same storage block with decoding codewords and external information (or channel information), which is a method with less FPGA resource occupation , an efficient storage solution with high decoding throughput. Background technique [0002] In modern digital communication systems, in order to ensure that various data can be transmitted reliably and effectively, error correction coding technology is often used. In recent years, with the development of digital communication and the emergence of various high-speed data services, it is more and more important to study and use error correction coding technology. Theoretical research shows that LDPC code is the best known error correction coding technology. The research results show that the code rate is 1 / 2 and the code length is 10 7 The performance of the irregular LDPC code ...

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Problems solved by technology

Theoretical research shows that LDPC code is the best known error correction coding technology. The research results show that the code rate is 1 / 2 and the code length is 10 7 The performance of the irregular LDPC code on the AWGN channel is only 0.04dB away from the capacity limit, and it is the error correction code closest to the Shannon limit so far. When Gallager invented the LDPC code in the early 1960s, due to the limited hardware The restrictions have not been applied. With the development of large-scale integrated circuit technology, LDPC codes have entered the stage of practical development from theoretical research.

Although LDPC codes have linear decoding complexity, when FPGA is used to implement LDPC decoder, it not only needs to occupy a lot of FPGA resources but also has low decoding throughput, which cannot meet the needs of high-speed data transmission.

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