Method and device for upgrading complex programmable logic device on line

A technology of programming logic and logic files, which is applied in the field of online upgrading of complex programmable logic devices, can solve problems such as difficulty in on-site program upgrades and high maintenance costs, and achieve the effects of convenient online updates, improved utilization, and reduced costs
CN101894029AInactive Publication Date: 2010-11-24ZTE CORP
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
ZTE CORP
Publication Date
2010-11-24
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The invention discloses a method and a device for upgrading a complex programmable logic device on line. The method comprises: storing a to-be-upgraded CPLD logic file in a binary format, and converting the to-be-upgraded CPLD logic file in the binary format into a JTAG time sequence electrical level when the CPLD is to be upgraded; according to a non-JTAG time sequence electrical level, simulating a standard JTAG time sequence electrical level by using a register; and gating a subordinate CPLD of the to-be-upgraded CPLD, and writing the standard JTAG time sequence electrical level into the to-be-upgraded CPLD to complete the online upgrade of the to-be-upgraded CPLD. When the method and the device are used, the CPLD device can be upgraded on line directly without cable sintering.
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Description

technical field

[0001] The invention relates to the field of software technology, in particular to a method and device for upgrading complex programmable logic devices online. Background technique

[0002] JTAG (Joint Test Action Group, Joint Test Action Group) is a standard for detecting PCB (Printed Circuit Board, printed circuit board) and IC (Integrated Circuit, integrated circuit board) chips formulated in 1985, and revised to IEEE (Institute) in 1990 of Electrical and Electronics Engineers, IEEE 1149.1 of the Institute of Electrical and Electronics Engineers. The IEEE1149.1 standard was first proposed by the JTAG organization, and finally approved and standardized by the IEEE. Therefore, the IEEE1149.1 standard is also called the JTAG debugging standard.

[0003] The standard JTAG interface is 4 lines, respectively: TMS (Test Mode Select, test mode selection), TCK (Test Clock, test clock), TDI (Test Data Input, test data input), TDO (Test Data Output, test data outpu...

Claims

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