Nth-order shift register capable of increasing driving power and method thereof

A technology of shift register and driving capability, which is applied in the direction of static memory, digital memory information, instruments, etc., and can solve problems such as inability to charge

Active Publication Date: 2015-06-03
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the prior art, the potential of the gate of the output stage transistor can only be charged to V due to the pull-up circuit before being pulled up by the coupling capacitor. GH -V th (V GH is the high voltage level of the clock signal, V th is the threshold voltage of the output stage transistor) cannot be charged to a higher potential
Therefore, the prior art can only increase the drive capability of some output stage transistors

Method used

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  • Nth-order shift register capable of increasing driving power and method thereof
  • Nth-order shift register capable of increasing driving power and method thereof
  • Nth-order shift register capable of increasing driving power and method thereof

Examples

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Embodiment Construction

[0039] Please refer to figure 1 , figure 1 A schematic diagram of an n-th stage shift register 100 capable of increasing driving capability is illustrated for an embodiment of the present invention. The nth shift register 100 includes a pull-down circuit 102 , a pull-up circuit 104 , a driver circuit 106 , a first capacitor 108 and a key pull-down circuit 110 . The pull-down circuit 102 uses the potential of the first node Q(n) and the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 to pull down the potential of the first node Q(n) to the output node of the shift register 100 of the nth stage The potential of G(n) and the potential of the output node G(n) of the n-th shift register 100 are pulled down to the reference low potential VSS. The pull-up circuit 104 is coupled to the pull-down circuit 102, and uses the output signal G(n-2) of the n-2th stage shift register to pull up the potential of the first node Q(n) for the first time, and th...

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PUM

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Abstract

The invention relates to a nth-order shift register capable of increasing driving power, which comprises a pull-down circuit, a pull-up circuit, a drive circuit, a first capacitor and a key pull-down circuit, wherein the pull-up circuit pulls up the potential of a first node of the nth-order shift register for the first time by utilizing the output signal of the (n-2)th-order shift register, and pulls up the potential of the first node for the second time by utilizing an output signal of the (n-1)th-order shift register or a first high-frequency clock signal; the first capacitor is used for pulling up the potential of the first node for the third time according to a second high-frequency clock signal; and the potential of the first node is used for driving the drive circuit.

Description

technical field [0001] The invention relates to a shift register, in particular to a shift register capable of increasing driving capability and reducing dynamic power consumption. Background technique [0002] In the previous technology, the shift register was fabricated on a glass substrate, and the process used was amorphous silicon or polysilicon process technology. Due to the low carrier mobility of the material, it is necessary to design a larger thin film transistor under a certain operating voltage. In order to effectively drive the scan lines of the panel. However, the parasitic capacitive effect generated by the larger thin film transistor is also greater, resulting in a significant increase in dynamic power consumption on the driving circuit. Therefore, making the shift register on the substrate can save the cost of the gate driving chip, but increases the consumption of dynamic power. [0003] In the prior art, the pull-up circuit of the shift register is used ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C19/28G09G3/20
Inventor 杨欲忠陈勇志林致颖徐国华
Owner AU OPTRONICS CORP
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