Reform buffer for vector data streams

Abstract

The invention discloses a reform buffer for vector data streams, which comprises a buffer memory stack, a control register, a status bit and a main control logic unit, wherein the buffer memory stack is used for temporarily storing data which comes from a DMA bus and is written into a vector memory VM or temporarily storing data which is read from the vector memory VM and required to be written into other spaces by the DMA bus; the control register is used for carrying out data configuration when the DMA bus starts to carry out data transmission; the status bit is used for recording that which row in the vector memory VM is mapped by each row in the buffer memory stack, and recording whether the row is effective; and the main control logic unit is used for overall control, when the DMA bus carries out the data transmission, the main control logic unit selects different buffer positions according to the control register, carries out corresponding data conversion, and selects whether to cancel or re-process the reading of the buffer when the data transmission is completed. The reform buffer has the advantages of simple and compact structure, low cost, wide application range, and good reliability, etc.

Description

technical field [0001] The present invention mainly relates to a processor using vector technology, in particular to a digital signal processor (Digital Signal Processor, DSP), between a DMA (Direct Memory Access, direct memory access) bus and a vector memory (Vector Memory, VM) The design and implementation method of the data transmission interface, especially the technical solution when the data needs to be relocated, compressed or expanded when moving between the DMA bus and the VM. Background technique [0002] With the development of 4G wireless communication technology and high-definition video image processing technology, vector processors have been widely used. The vector processor develops the data-level parallelism of the application through simultaneous processing of multiple parallel vector operation units. How to provide sufficient data bandwidth for the vector operation unit is an important link in the design of the vector processor. Due to the lack of data lo...

AI Technical Summary

Problems solved by technology

At present, there is no published literature related to the vector data flow oriented in the case of a single-port SRAM in the VM, and can effectively balance the bandwidth difference between the DMA bus and the VM, and provide data flow position reorganization, compression or expansion, etc. Design issues of the buffer structure of the reorganization function

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