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Test method and system of multiple paths of E1 ports for realizing STM-1 interface

A technology of STM-1 and test method, applied in the direction of transmission system, digital transmission system, data exchange network, etc.

Inactive Publication Date: 2014-03-19
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Another object of the present invention is to provide a kind of test system that realizes the multi-channel E1 mouth of STM-1 interface, is used to solve the problem that multi-channel E1 mouth tests simultaneously on the STM-1 interface

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  • Test method and system of multiple paths of E1 ports for realizing STM-1 interface
  • Test method and system of multiple paths of E1 ports for realizing STM-1 interface
  • Test method and system of multiple paths of E1 ports for realizing STM-1 interface

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Embodiment Construction

[0030] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0031] figure 1 Show the schematic flow chart of the test method of the multi-channel E1 mouth of STM-1 interface that the present invention provides, as figure 1 Shown:

[0032] Step S101, establish a one-to-one correspondence between each E1 port on the STM-1 interface on the line side of the intermediate device and the N-way E1 ports on the branch side of the intermediate device, and each E1 port in the series test channel of the N-way E1 ports passes through The STM-1 interface on the line side of the intermediate device establishes a one-to-one correspondence with all the E1 ports of the STM-1 interface of the device under test, and the one-to-one c...

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Abstract

Disclosed are a method and system for testing multiple channels of E1 ports of an STM-1 interface. The method includes: establishing a one-to-one correlation between each E1 port of the STM-1 interface at the intermediate device line side and N channels of E1 ports at the intermediate device branch side; connecting the N channels of E1 ports at the intermediate device branch side in series so as to form a testing channel of N channels of E1 ports connected in series and connecting an SDH tester, and docking the STM-1 interface at the intermediate device line side with the STM-1 interface of the device under test; and testing by the SDH tester all the E1 ports of the STM-1 interface of the device under test via the testing channel of N channels of E1 ports connected in series simultaneously, wherein N is an integer greater than or equal to 2. The present invention monitors each E1 port of multiple channels of E1 ports on the STM-1 interface by means of the network administrator, achieving synchronous testing of multiple channels of E1 ports on the STM-1 interface.

Description

technical field [0001] The invention relates to the E1 port test in the channelized STM-1 interface, in particular to a test method and system for realizing the multi-channel E1 port of the channelized STM-1 interface. Background technique [0002] When testing a channelized STM-1 interface, the bit error performance test of the interface is generally performed by testing one of the 63 E1 ports of the channelized STM-1 interface. However, due to differences in physical wiring and clock distribution, Each of the 63 E1 ports of the channelized STM-1 interface has its own characteristics. Only testing one or a few of them does not represent the bit error performance of all channels of the 63 E1 ports of the channelized STM-1 interface. It cannot indicate that all channels of the 63 E1 ports of the channelized STM-1 interface can send and receive packets normally, so under strict test requirements, it should be a channelized STM-1 interface (for simplicity, the channelized STM-1...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/26
CPCH04L12/2697H04L43/50
Inventor 申雅玲
Owner ZTE CORP