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Clock gating system and method

A technology of clock gating and clock gating, applied in electrical components, sustainable buildings, climate sustainability, etc., can solve problems such as power consumption, and achieve the effect of reducing power consumption and reducing occupied area

Active Publication Date: 2011-04-13
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the clock gating unit used to perform clock gating also consumes power

Method used

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  • Clock gating system and method
  • Clock gating system and method
  • Clock gating system and method

Examples

Experimental program
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Embodiment Construction

[0019] see figure 1 , depicts an illustrative embodiment of a system to generate a gated clock signal and is generally designated 100 . System 100 includes a clock gating unit 102 coupled to a gated circuit 104 . The clock gating unit 102 receives a clock input 106 and a first input 108 . Clock gating unit 102 may also receive one or more additional inputs, such as second input 110 . The clock gating unit 102 provides a gated clock signal 112 to the gated circuit 104 . The clock gating unit 102 includes a clock gating circuit 128 .

[0020] Clock gating circuit 128 contains input logic circuit 114 , which is coupled to internal enable node 107 . Keeper circuit 120 and gating element 122 are also coupled to internal enable node 107 . The keeper circuit 120 includes at least one switching element 128 that is responsive to the gated clock signal 112 . Because switching element 128 is responsive to gated clock signal 112 rather than the input clock signal received at clock ...

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PUM

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Abstract

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Application No. 61 / 048,661, filed April 29, 2008, which is hereby incorporated by reference in its entirety and claims priority. technical field [0003] The present invention generally relates to clock gating. Background technique [0004] Advances in technology have resulted in ever smaller and more powerful personal computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices, that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data packets over wireless networks. In addition, many such wireless telephones include other types of devices incorpo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/04H03K19/00
CPCY02B60/50
Inventor 马丁·圣劳伦特巴萨姆·贾米尔·穆赫德保罗·巴西特
Owner QUALCOMM INC