A CMP-free planarization process suitable for gate-last process

Abstract

A preparation process suitable for gate-last process without CMP planarization, using photoresist commonly used in CMOS process, after dilution, it has good fluidity to fill the bottom of the uneven pattern, so that the pattern surface after spin coating Basically flat. Using photoresist as a carrier, using the speed difference between photoresist and LTO, the LTO of the raised pattern is shoveled off, and the active area of ​​the device is protected by residual glue from erosion, and a nearly flat surface is obtained. ; Repeat the glue coating again, so that the photoresist and LTO will be etched back at the same rate to achieve the purpose of full planarization. Then etch back the dielectric until the dummy gate electrode is exposed, remove the polysilicon dummy gate electrode, and deposit the required metal gate film. The invention does not need to add special equipment, has simple technology, is easy to monitor, has better compatibility with CMOS technology, and provides convenience for the integration of replacement gate in the last gate technology.

Description

technical field [0001] The invention belongs to a nanoscale semiconductor device preparation process, relates to a non-CMP planarization process technology, and is a necessary means for preparing a nanoscale gate-last process CMOS (complementary metal oxide semiconductor) device. technical background [0002] The current development of integrated circuits has entered the technology generation of 45nm node and below. In order to reduce the serious gate tunneling leakage current of ultra-thin gate dielectric and eliminate the depletion effect of polysilicon gate, high dielectric constant (K) gate dielectric / metal gate electrode is adopted. It is imperative to replace the traditional SiON gate dielectric / polysilicon gate electrode structure with an integrated structure. The high-K gate dielectric / metal gate structure is divided into gate-first process and gate-last process. Since the gate-last process is an integrated process of gate process after the source and drain are forme...

AI Technical Summary

Problems solved by technology

[0003] In order to overcome the shortcomings of high cost, expensive equipment and difficult control of the CMP planarization process in the gate-last process, the present invention provides a low-cost planarization process without a CMP process, which is simple in process and easy to monitor, and is comparable to the CMOS process Good compatibility, which facilitates the integration of replacement gates in the gate-last process

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