Method for simulating cores of multi-core processor by adopting time division multiplex

A multi-core processor, time division multiplexing technology, applied in machine execution devices, concurrent instruction execution, etc., can solve the problems of long hardware programming development cycle, low flexibility and applicability, and high programming and debugging difficulty, and improve hardware integration. , avoid problems and the effect of consistency, saving hardware overhead

Active Publication Date: 2011-05-25
TSINGHUA UNIV
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Problems solved by technology

However, purely using hardware for processor simulation also has several fatal problems: First, the development cycle of hardware programming is long, programming and debugging are difficult, and there are also problems of low flexibility and applicability
At the same time, hardware simulation of such instructions is a very complicated operation. Such a design can reduce development costs, but the cost is still high.

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  • Method for simulating cores of multi-core processor by adopting time division multiplex
  • Method for simulating cores of multi-core processor by adopting time division multiplex
  • Method for simulating cores of multi-core processor by adopting time division multiplex

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Embodiment Construction

[0028] The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0029] The present invention uses an N-segment pipeline to simulate the core of a multi-core processor. Different from the pipeline of the processor itself, the purpose of using the pipeline here is mainly to improve the integration and ensure the flexibility of the simulated processor when it is compatible with other instruction sets.

[0030] Such as figure 1 Shown, method of the present invention comprises the following steps:

[0031] S1. On a single FPGA board, the execution process of each instruction of each core of the multi-core processor is divided into N steps, and each step is executed using a pipeline segment, and N pipeline segments form a pipeline;

[0032] ...

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Abstract

The invention discloses a method for simulating cores of a multi-core processor by adopting the time division multiplex, which is characterizing by simulating N cores of the multi-core processor according to M processor examples, wherein the N is more than the M. The method comprises the following steps: S1, dividing the process of executing each instruction of each core of the multi-core processor into N steps on a single FPGA (field programmable gate array) plate, wherein each step is executed by one flow segment, and N flow segments form one flow line; and S2, sending the instructions of the N cores of the multi-core processor to the flow line sequentially and consecutively to execute the instructions. The invention realizes the simulation of the cores of the multi-core processor by using fewer FPGA resources.

Description

technical field [0001] The invention relates to the field of computer architecture, in particular to a method for realizing multi-core processor core simulation based on time division multiplexing. Background technique [0002] In the research process of computer architecture, a key link is to verify the correctness of the design and evaluate the performance of the architecture through simulation. There are currently two main simulation methods, one is to use software to simulate the system, and the other is to use hardware to simulate the system. Due to the relatively high cost of hardware equipment, the cost of software simulation equipment is lower, and software implementation is relatively simpler than hardware implementation, and it is also easy to modify. As the speed of the processor doubles every 18 months according to Moore's Law, software does not Any changes need to be made, and the simulation speed will be increased accordingly. However, in recent years, the ma...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 郑纬民张悠慧钱自强苏格林
Owner TSINGHUA UNIV
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