IGBT (Insulated Gate Bipolar Translator) device structure and preparation method thereof

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure which comprises an N type high resistance rate region melting type or epitaxial silicon substrate formed on a silicon base plate. An N type doping region with a medium concentration which is higher than the concentration of the substrate, a P type well, an N type epitaxial silicon layer and a grate zone of an MOS (Metal Oxide Semiconductor) structure are introduced in an active region of the device with the silicon substrate. P type doping and impurity diffusion are carried out on the epitaxial silicon layer between grooves at a depth part close to the bottoms of the grooves so as to form a P type MOS well region. Contact holes are etched in a transmitting region and a polysilicon gate zone, metal is deposited, and ohmic contact is formed between the metal, silicon and a polysilicon highly-doped region. The invention also provides a preparation method of the IGBT (Insulated Gate Bipolar Translator) device structure. The preparation method comprises the following steps of high temperature diffusion propulsion, annealing, activation and the like.

Description

technical field [0001] The invention relates to a trench type IGBT device structure and preparation method with high anti-latch characteristics, which belongs to the semiconductor manufacturing process. Background technique [0002] The trench IGBT device is an advanced IGBT device type, which moves the MOS control structure from the silicon surface to the vertical channel, and eliminates the parasitic JFET effect of the planar IGBT device, so that it can achieve the same device current capability. Under the same process cost, the device area can be reduced, and the cost performance of the device can be improved. [0003] However, the usual trench type IGBT has poor anti-latch-up characteristics, and the safe operating area (SOA) is also narrow. The reason is that if an additional The P+ deep well structure is used to prevent the latch-up caused by the parasitic NPN tube effect, and the protruding P+ deep well can easily pinch off the surrounding N- substrate with extremely...

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Problems solved by technology

[0003] However, the usual trench type IGBT has poor anti-latch-up characteristics, and the safe operating area (SOA) is also narrow. The reason is that if an additional The P+ deep well structure is used to prevent the latch-up caused by the parasitic NPN tube effect, and the protruding P+ deep well can easily pinch off the surrounding N- substrate with extremely low doping concentration, which will increase the series resistance of the parasitic JFET tube. This negates the advantage of trench devices over planar devices

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