Manufacture method of power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention relates to a manufacturing method of a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). A first conductive type epitaxial layer is formed on a first conductive type substrate. A second conductive type main body layer is formed in the epitaxial layer. A plurality of mask patterns are formed on the substrate. A plurality of ditches are formed in the main body layer and the epitaxial layer between the mask patterns. An oxide layer is formed on the surface of each ditch. A conductor layer is formed in each ditch. The process of the mask pattern is reduced to shortenthe line width of each mask pattern. Two first conductive type source areas are formed in the body layers at two sides of each ditch based on the reduced mask patterns as masks. A plurality of dielectric patterns are formed on the conductor layer and between the reduced mask patterns. The reduced mask patterns are removed.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor element, and in particular to a manufacturing method of a power metal-oxide-semiconductor field effect transistor (power metal-oxide-semiconductor field effect transistor; powerMOSFET). Background technique [0002] Power MOSFETs are widely used in switching (power switch) components, such as power supplies, rectifiers, or low-voltage motor controllers. Generally speaking, power MOSFETs adopt a vertical structure design to increase device density. It utilizes the backside of the wafer as the drain, and fabricates the sources and gates of multiple transistors on the front side of the wafer. Since the drains of multiple transistors are connected in parallel, the current they can withstand can be quite large. [0003] As the integration level of power MOSFETs increases day by day, the size of power MOSFETs also shrinks accordingly. Therefore, the misalignment between the contact...

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Problems solved by technology

Therefore, misalignment between the contact hole and the trench of the power MOS field effect transistor is easy to occur, which in turn affects the performance of the device.

For example, the alignment deviation of the contact hole to the trench will affect the variation of the channel turn-on resistance (Ron) and threshold voltage (Vth), thereby limiting the reduction of the cell pitch

[0004] In addition, the operating loss of power MOS field effect transistors can be divided into two categories: switching loss and conducting loss. Among them, due to the input capacitance C iss The resulting switching losses increase with operating frequency

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