Deleted graph-based parallel decomposition method for circuit sparse matrix in circuit simulation

A sparse matrix, circuit simulation technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of few parallel software and few parallel versions of general-purpose multi-core CPU platforms, etc., to ensure a high degree of parallelization , the effect of acceleration

Active Publication Date: 2011-08-17
TSINGHUA UNIV
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Problems solved by technology

[0008] Although there are already many software packages based on LU decomposition, such as SuperLU, KLU, PARDISO, UMFPack, etc., there are dozens of software in total, but among these software, there are very few parallel versions, and the parallel software for general multi-core CPU platforms is even more very few

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  • Deleted graph-based parallel decomposition method for circuit sparse matrix in circuit simulation
  • Deleted graph-based parallel decomposition method for circuit sparse matrix in circuit simulation
  • Deleted graph-based parallel decomposition method for circuit sparse matrix in circuit simulation

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[0044] In order to achieve the above object, the present invention adopts following technical scheme, and its implementation steps are:

[0045] Step 1: Perform symbol analysis on the input n×n circuit matrix A, and complete the calculation of the non-zero element structure of n columns of L and U in sequence from the first column to the nth column;

[0046] Step 2: Utilize the non-zero structure of the U matrix obtained in step 1, and obtain the elimination graph through the earliest start algorithm;

[0047] Step 3: Based on the non-zero structure of L and U obtained in step 1 and the elimination graph obtained in step 2, perform parallel LU numerical decomposition. In the numerical decomposition process, two different parallel methods are used: group parallelism and pipeline parallelism. The two parallel methods are dynamically selected during the numerical decomposition process according to the structure of the elimination graph. Thus, the parallel LU decomposition proce...

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Abstract

The invention provides a deleted graph-based parallel decomposition method for a circuit sparse matrix in circuit simulation, belonging to the field of electronic design automation (EDA). The method is characterized in that a deleted graph is extracted from a symbolic analysis result of a circuit matrix for representing data independence in a lower-upper (LU) decomposition process; and two different parallel methods, namely a group parallel method and stream-line parallel method, are used according to different structures of the deleted graph, so that the calculation time of LU decomposition is reduced, and the speed of circuit simulation is accelerated. Test results on a series of test circuit matrixes indicate that the LU decomposition speed according to the invention is 1.66-7.72 times faster than that of LU decomposition software KLU when the count of parallel threads is 1-8.

Description

technical field [0001] The invention relates to a parallel LU decomposition method based on an elimination graph for a circuit sparse matrix during circuit simulation, and belongs to the technical field of electronic design automation (EDA). Background technique [0002] In scientific computing, solving the linear equation system Ax=b (the form of Ax=b is as figure 1 As shown, A is an n×n matrix, b and x are both n-dimensional column vectors, A and b are known, and x is unknown to be found) has a pivotal position. The solution methods of Ax=b can be mainly divided into two categories: iterative method and direct method. Iterative methods such as Jacobi iterative method, Gauss-Seidel iterative method, super-relaxed iterative method, etc., all set the initial value of a set of solutions first, and then iterate through an iterative formula to make the solution gradually approach the real solution. close, the iteration converges when the error is less than a given value. Howe...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 汪玉陈晓明武伟杨华中
Owner TSINGHUA UNIV
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