High-density system-in-a-package method

A system-in-package, high-density technology

Inactive Publication Date: 2011-08-17
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function. However, with the trend of semiconductor products becoming thinner and smaller an

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[0019] In the following description, many specific details are explained in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar popularizations without violating the connotation of the present invention. Therefore, the present invention is not limited by the specific implementation disclosed below.

[0020] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, the schematic diagrams are only examples, which should not limit the scope of protection of the present invention.

[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] reference figure 1 , Shows a schematic flow chart of an embodiment of the high-density system-in-package method of the present in...

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Abstract

The invention relates to a high-density system-in-a-package method comprising the following steps of: supplying a base plate; forming at least one group of wiring packaging layers on the base plate, wherein the step of forming at least one group of wiring packaging layers includes the steps of sequentially forming an adhering layer, a packaging layer and a wiring layer on the base plate; forming lead bonding packaging layers on the tail group of wiring packaging layers, wherein the step of forming the lead bonding packaging layers includes the steps of sequentially forming an adhering layer, a metal lead bonding layer and the packaging layer; and bumping below the base plate. Compared with the prior art, by adopting the high-density system-in-a-package method disclosed by the invention, a final packaging product containing an integral system function but not a single chip function can be formed, the factor of the interference among the resistance, the inductance and the chip inside a system is reduced; and besides, by means of the high-density system-level packaging method, a more complicated multilayer interconnected structure can be formed, and the wafer system-in-a-package with higher integrated degree is realized.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a high-density system-in-package method. Background technique [0002] With the continuous development of integrated circuit technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high performance and high reliability. The integrated circuit packaging not only directly affects the performance of integrated circuits, electronic modules and even the whole machine, but also restricts the miniaturization, low cost and reliability of the entire electronic system. With the gradual reduction of the size of the integrated circuit chip and the continuous improvement of the integration level, the electronic industry has put forward higher and higher requirements for the integrated circuit packaging technology. [0003] A package substrate is disclosed in Chinese Patent No. CN1747156C. The packaging substrate includes: a substrate, the sub...

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Application Information

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IPC IPC(8): H01L21/50H01L21/56H01L21/768
CPCH01L2924/15311
Inventor 陶玉娟石磊
Owner NANTONG FUJITSU MICROELECTRONICS
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