High-density chip system-in-package structure

Abstract

The invention provides a high-density chip system-in-package structure, which comprises a chip, a passive device and a solidified package material layer, wherein the chip and the passive device are provided with a functional surface respectively; and the solidified package material layer is positioned on the sides, away from the functional surfaces, of the chip and the passive device, and packages the chip and the passive device. The high-density chip system-in-package structure increases the integration level of the package, reduces interference factors such as in-system resistance, in-system inductance and the like, and can meet the requirements of light weight, low thickness, shortness and small volume on semiconductor packaging.

Description

Technical field [0001] The invention relates to semiconductor technology, in particular to a high-density system-on-chip packaging structure. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology in which the entire wafer is packaged and tested and then cut to obtain a single finished chip. The packaged chip size is exactly the same as the bare chip. Wafer-level chip size packaging technology has completely subverted traditional packaging such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier. It conforms to the market’s increasing demand for microelectronic products. Small, short, thin and low price requirements. The chip size after wafer-level chip size packaging technology has reached a high degree of miniaturization, and the chip cost has been significantly reduced as the chip size decreases and the wafer size increases. Wafer-level chip size packaging technology is a technology that can integrate IC design, wafer manufacturin...

AI Technical Summary

Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function

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