Phase difference detection method, device and circuit in phase-locked loop circuit

Abstract

The embodiment of the invention discloses a phase difference detection method, device and circuit in a phase-locked loop circuit, and is used for improving the precision of phase difference detection. The method comprises the following steps: setting phase difference of a first clock signal and a clock signal output by the first clock signal in a first phase-locked loop circuit, inputting a second phase-locked loop circuit as a feedback clock signal; detecting whether a phase locking signal in output signals of a second phase-locked loop circuit exists; if the phase locking signal exists, taking the phase difference as the phase difference of the first clock signal and a second clock signal in the second phase-locked loop circuit; and if the phase locking signal does not exist, regulating the set phase difference until a phase locking signal in the output signals is detected.

Description

technical field [0001] The present invention relates to the field of electronic technology, in particular to a phase difference detection method, device and circuit in a phase-locked loop. Background technique [0002] Nowadays, the detection of chip signal phase difference is becoming more and more important, especially in systems that require precise time synchronization, the accuracy of phase difference detection becomes the key to the success of time synchronization. Moreover, with the improvement of system requirements for fault alarm accuracy, phase The application of detection technology in system fault detection is also important. [0003] At present, the method of detecting the phase difference of the internal signal of the element programmable logic gate array (FPGA, Field Programmable Gate Array) usually uses a detection clock signal with a high operating frequency to detect two low-frequency detected clock signals that need to compare phases. The clock signal is...

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Problems solved by technology

[0004] In the above prior art, since the detection clock signal has a multiple relationship with the frequency of the detected clock signal, the frequency of the detection clock signal is represented by F2, the frequency of the detected clock signal is represented by F1, and the measurable phase difference value is represented by n It means that the relationship between the three can be expressed as F2=F1×360 / n, assuming that the frequency of the detected clock signal is 30Mhz, when the frequency of the detected clock signal is 240Mhz, which is 8 times the frequency of the detected clock signal , the 45-degree phase difference can be detected. It can be seen that when the frequency of the detected clock signal increases, the operating frequency of the detected clock signal needs to be multiplied, but the operating frequency range of the detected clock signal is limited by the chip design. In the prior art, the detected clock signal The operating frequency of the signal does not exceed 400 MHz, therefore, the measurement accuracy is affected

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