Memory provided with input voltage conversion unit

A technology of converting unit and input voltage, applied in the field of memory

Active Publication Date: 2011-09-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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  • Memory provided with input voltage conversion unit
  • Memory provided with input voltage conversion unit
  • Memory provided with input voltage conversion unit

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Embodiment Construction

[0038] It can be seen from the background technology that the existing memory such as figure 1 As shown, it generally includes n rows and m columns of NMOS transistors arranged in an array, wherein the gates of the NMOS transistors in each row are connected to a word line, and the NMOS transistors in n rows are respectively connected to n word lines. The drains of the NMOS transistors in each column are connected to one bit line, and the NMOS transistors in m columns are respectively connected to m bit lines. Such as figure 2 As shown, during the read operation, the sources of all NMOS transistors are coupled to zero voltage (ground), and the higher the voltage of the word line and the bit line, the greater the read operation current. However, once the voltage of the word line and the bit line is too high, the current of the read operation is too large, which will cause damage to the memory cell.

[0039] For this reason, the inventor of the present invention proposes a mem...

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Abstract

The invention provides a memory provided with an input voltage conversion unit. The memory comprises storage units, word lines, bit lines, a word line input end, a bit line input end, a word line clamping circuit and a bit line clamping circuit, wherein the storage units are arranged in an array manner; the same-row storage units are connected to one of the work lines; the same-line storage units are connected to one of the bit lines; the word line input end inputs a first voltage; the bit line input end inputs a second voltage; the word line clamping circuit is used for clamping the first voltage to a third voltage and outputting the third voltage to the word lines; the second voltage is smaller than the first voltage; the bit line clamping circuit is used for clamping the second voltage to a fourth voltage and outputting the fourth voltage to bit lines; and the fourth voltage is smaller than the second voltage. Therefore, the crosstalk problem caused by excessive reading current is avoided, and the power consumption is saved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory with an input voltage conversion unit. Background technique [0002] With the development of integrated circuits, memory devices are more and more widely used in products. Memory is usually divided into read-only memory (ROM) and random access memory (RAM), in which read-only memory is divided into: mask programming (ROM), programmable (PROM), erasable programmable ROM (EPROM) and electrically programmable Erase Programmable ROM (EEPROM). Random access memory is divided into: static random access memory (SRAM) and dynamic random access memory (DRAM). With the development of smart products, memory devices are installed in a large number of smart products, such as MP3, MP4, mobile phones, etc., which also makes the performance of memory play a vital role in smart products. [0003] Existing memories generally include memory cells arranged in an array, a row of memory cel...

Claims

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Application Information

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IPC IPC(8): G11C16/02G11C16/10G11C16/06
Inventor 杨光军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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