Package structure

Abstract

A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal. the heat generated in bottom chip and top die may be easily dissipated to form a low stress and reduce the possibility of the breakage of the bottom chip.

Description

technical field [0001] The present invention relates to an integrated circuit package, in particular to a three-dimensional integrated circuit (three-dimensional integrated circuit, 3DIC) package using a dummy wafer. Background technique [0002] With the development of semiconductor technology, semiconductor chips are becoming smaller and thinner. As a result, semiconductor packaging becomes more compact. [0003] Packaging technology can be divided into two types. One type is commonly referred to as chip-level packaging, in which chips are diced from a wafer prior to packaging. The advantage is that only known-good-dies are packaged. Another advantage of this packaging technology is the possibility of forming a fan-out chip package, which means that the I / O pads on the chip can be redistributed in an area larger than the chip, so that the package on the chip surface can be increased. The number of I / O bond pads formed. [0004] After the chip is bonded to a wafer, a s...

AI Technical Summary

Problems solved by technology

However, usually molding materials have low thermal conductivity, resulting in low heat-dissipating capabilities of 3D integrated circuits

In addition, heat dissipation becomes a serious problem as more heat is generated in 3D integrated circuits as they become more compact

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