Power supply clamping circuit

Abstract

The invention provides a power supply clamping circuit which comprises a VDD, a GND, a clamping unit and a step-down unit. The power supply clamping circuit is characterized in that: the clamping unit and the step-down unit are parallelly connected between the VDD and the GND; The step-down unit is connected with the clamping unit; when the VDD is affected by ESD static pulse, trigger voltage of the clamping unit is reduced by the step-down unit and clamping restriction is performed on electric potential of the VDD by the clamping unit. Compared to the prior art, the power supply clamping circuit provided by the invention possesses lower trigger voltage, can timely response to the ESP static pulse and bear higher working voltage so that a protection demand to the clamping of the VDD when there is a large energy pulse can be satisfied.

Description

Technical field [0001] The invention relates to the field of integrated circuit electrostatic protection circuit design, in particular to a power clamp circuit for electrostatic protection circuits. Background technique [0002] Integrated circuits are susceptible to destructive electrostatic discharge (ESD) during manufacturing or use during manufacturing, assembling, testing, or final applications, so that the integrated circuits are damaged by static electricity. Therefore, ESD protection circuits are usually formed in integrated circuits, so that the input / output pad (I / O pad) is coupled with a discharge unit that can discharge the static electricity on the I / O pad, so that the I / O can be The static electricity on the pad is released, reducing the damage caused by static electricity to the integrated circuit. For example, an electrostatic discharge (ESD) protection circuit is disclosed in the patent document with the application number "01807873.7". In addition, there are a...

AI Technical Summary

Problems solved by technology

[0005] The problem with the above clamping circuit is that only relying on a single GGNMOS, the clamping capability of the power line VDD is small, so a structure of multiple GGNMOSs connected in parallel is usually used

[0008] The problem of the above clamping circuit is: the base width of the parasitic NPN transistor from the power line VDD to the ground line GND is relatively long, so that the trigger conduction voltage of the parasitic NPN transistor is too high

Reduced sensitivity to ESD electrostatic pulses. If the ESD electrostatic pulse cannot be responded in time, the clamping circuit may not work, and the chip will be damaged by static electricity.

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