Method for monitoring formation process of metallic silicide layer
A metal silicide layer and process technology, which is applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc., can solve the problem of no metal silicide layer formation process, and achieve the effect of improving efficiency
Active Publication Date: 2011-10-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
However, the method does not effectively monitor the metal silicide layer formation process, especially the metal silicide layer formation process that forms a metal silicide layer on the surface at the junction of the p-type doped region and the n-type doped region.
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[0023] It can be known from the background art that currently there is a relatively lack of an effective monitoring method for the formation process of the metal silicide layer. The inventors conducted research on the above problems and found that the current monitoring method for the formation process of the metal silicide layer is mainly aimed at the n-type doped active region and the p-type doped active region with the smallest design size, or the n-type doped active region with the smallest design size. Type doped polysilicon, p-type doped polysilicon four structures. If there is an alternation of n-type doping and p-type doping, it is difficult to monitor effectively by existing methods. However, the formation of the metal silicide layer at the n / p junction is the most difficult, and this situation is more prominent in smaller and smaller design dimensions, and monitoring is even more important.
[0024] The inventors of the present invention conducted further research o...
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The invention relates to a method for monitoring the formation process of a metallic silicide layer. The method comprises the following steps: a target resistance value range is provided; a semiconductor substrate is provided, wherein the semiconductor substrate comprises n-type doping areas and p-type doping areas arranged alternately along the surface of the semiconductor substrate, an interface is arranged between the adjacent n-type doping area and p-type doping area. a metallic silicide layer is formed on the surfaces of the n-type doping area and p-type doping area; the metallic silicide layer intersects with the interface of the adjacent n-type doping area and p-type doping area; the resistance value of the metallic silicide is measured and is compared with the target resistance value range; if the resistance value is within the target resistance value range, the metallic silicide layer formation process satisfies the requirements, otherwise, the metallic silicide layer formation process does not satisfy the requirements. Correspondingly, the invention also provides the structure applicable to the method for monitoring the metallic silicide layer of the formation process. The method in the invention can be used for effectively monitoring the formation process of the metallic silicide layer.
Description
technical field [0001] Embodiments of the present invention relate to semiconductor technology, and in particular to a method for monitoring the formation process of a metal silicide layer. Background technique [0002] In the semiconductor manufacturing process, in order to reduce the contact resistance between the interconnection structure and other devices, a metal silicide layer is usually formed on the surface of the device. In order to form the metal silicide layer, a dielectric layer is first formed on the surface of the device, and then the dielectric layer on the surface of the area where the metal silicide layer needs to be formed is etched away to expose the area used to form the metal silicide layer; subsequently, in Continue to deposit metal material and protective layer on the surface of the device, the protective layer prevents the oxidation of the metal material in the subsequent annealing treatment; then, the metal material is fused with the silicon on the s...
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Login to View More IPC IPC(8): H01L21/00H01L21/66H01L23/544
Inventor 江红
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP