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Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof

A technology of chip package and production method, which is applied in the field of multi-circle arrangement carrierless double IC chip package, to achieve the effect of avoiding cross wire and open circuit, short heat conduction distance and reducing influence

Active Publication Date: 2013-12-04
TIANSHUI HUATIAN TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current four-sided flat no-lead package cannot meet the needs of high-density, multi-I / O packaging due to fewer pins, that is, fewer I / Os. At the same time, the bonding wire is long, which affects high-frequency applications.
Moreover, the general thickness of QFN is controlled at 0.82mm~1.0㎜, which cannot meet the needs of ultra-thin packaging products.

Method used

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  • Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof
  • Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof
  • Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] (1), wafer thinning

[0062] Using 8-inch to 12-inch thinning machine, adopts rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 6μm / s, fine grinding speed: 1.0μm / s; the thickness of the wafer without bumps is 100μm, the rough grinding speed is 2μm / s, the fine grinding speed is 0.8μm / s, and the chip warpage prevention process is adopted.

[0063] (2), scribing

[0064] Wafers ≤8 inches use DISC 3350 double-knife dicing machine, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s.

[0065] (3), one-time loading

[0066] IC chips 7 with a carrier frame and no bumps are used for one-time chipping, and conductive adhesive 5 is used for one-time chipping. The equipment and process used for chipping and baking are the same as those of ordinary QFN.

[0067] (4), pressure welding

[0068] Carry out wire bonding for the ...

Embodiment 2

[0088] (1), wafer thinning

[0089] Using 8-inch to 12-inch thinning machine, using rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 3μm / s, fine grinding speed: 0.6μm / s; the thickness of the wafer without bumps is 100 μm, the rough grinding speed is 4 μm / s, the fine grinding speed is 0.4 μm / s, and the chip warpage prevention process is adopted.

[0090] (2), scribing

[0091] Wafers ≤8 inches use DISC 3350 double-knife dicing machine, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s.

[0092] (3), one-time loading

[0093] Adopt QFN adhesive film (6) and IC chip (7) without concave and convex points, use a core loading machine with adhesive film (6) bonding process, and use a flip chip loading machine for the secondary core of the double chip. The bumps (4) of the IC chip (3) with bumps are dipped with solder (2) and plac...

Embodiment 3

[0115] (1), wafer thinning

[0116] Using 8-inch to 12-inch thinning machine, using rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 3μm / s, fine grinding speed: 0.6μm / s; the thickness of the wafer without bumps is 100 μm, the rough grinding speed is 4 μm / s, the fine grinding speed is 0.4 μm / s, and the chip warpage prevention process is adopted.

[0117] (2), scribing

[0118] Wafers ≤8 inches use DISC 3350 double-knife dicing machine, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s.

[0119] (3), one-time loading

[0120] IC chips 7 with a carrier frame and no bumps are used for one-time chipping, and conductive adhesive 5 is used for one-time chipping. The equipment and process used for chipping and baking are the same as those of ordinary QFN.

[0121] (4), pressure welding

[0122] With embodiment 1.

[0123] (5), t...

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Abstract

A multi-turn arrangement double IC chip package and a production method thereof, the multi-turn arrangement double IC chip package includes a multi-turn QFN lead frame with a carrier, inner leads, IC chips and a plastic package. The production methods are as follows: thinning, scribing, one-time die-on, bonding, two-time flip chip-on-die, underfill & curing, plastic encapsulation and post-curing, printing, pin separation, electroplating, product separation, product testing, packaging into library. The multi-turn QFN lead frame design of the present invention can increase more than 40% of the pin number design of the single-row lead frame with the same area, and meets the needs of high-density and multi-I / O packaging. Few and short wires, short heat conduction distance, and good heat dissipation; flip-chip, the capacitance and inductance between bumps and pins are much smaller than the capacitance and inductance of bonding wires between chip pads and pins, reducing the need for high-frequency applications Influence, the thickness of QFN can be reduced to less than 0.5mm, avoiding wire crossing and open circuit, improving the test yield and reliability.

Description

technical field [0001] The invention relates to the technical field of electronic information automation components manufacturing, in particular to four-sided flat leadless IC chip packaging, specifically a multi-circle arrangement carrierless dual IC chip package, and the invention also includes a production method for the package . Background technique [0002] In recent years, with the rapid development of portable electronic components in the field of mobile communications and mobile computers, small packaging and high-density assembly technology has been greatly developed; at the same time, a series of strict requirements have been put forward for small packaging technology, such as requirements The package dimensions should be kept as small as possible, especially if the package height is less than 1 mm. The connection reliability after packaging is improved as much as possible, suitable for lead-free soldering (protecting the environment) and effectively reducing co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L21/60
CPCH01L2924/181H01L2924/30107H01L2224/16145H01L2224/32145H01L2224/32245H01L2224/45144H01L2224/45147H01L2224/48247H01L2224/73204H01L2224/73265H01L2224/49433H01L2924/00H01L2924/00014H01L2924/00012H01L2924/00011
Inventor 朱文辉慕蔚李习周郭小伟
Owner TIANSHUI HUATIAN TECH
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